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| Release | Date | Changes |
| 6.00.02 BETA checksum PN 123635SW |
19/9/95 E900 |
Contents All base chipset initialisation for OPB, OMC, SIO and Combo as per Tech. Ref. Version 0.2 - 18 Sept. 1995 P6 initialisation for Cache, A0 OPB bug and Fast Strings for B0 P6 included. Supports A, AV and B builds of the motherboard. Selection of Secondary IDE controller is via setup option to support unmodified AV, modified AV and B. This setup option will be removed or blanked in later releases. Support for GD5436. A separate version of the BIOS is available with support for GD5434 (IMAGE.BIN) in earlier prototypes, but should not be required for shipping. Full Combo device configuration via PnP for Windows95. (Win95 SCT BIOSTEST Passes.) IDE modes 0-4 supported on Disks and CD-ROMs. OEM Custom sign-on supported. PCI Bus masters are reset on warm boot. Supports Synchronous and Asynchronous builds of motherboard and core clocks 50Mhz, 60Mhz and 66Mhz. Supports Via IDE Chips VT83C561 and VT83C571 in ISA Compatibility mode. Supports Diamond (2 PCI Slot) and Cosworth (3 PCI Slot) Risers. Date and Time in Setup should be in UK format. Displays detected max. IDE Device mode in setup and allows for limiting to compatibility mode 0. Supports Colour and Monochrome monitors. Exclusions PCI-PCI bridge support. C2 Security. Power Saving. Proper name for P6 on setup screen. Includes no special support for EDO DIMMS. Testing Limited testing on Cosworth AV 50Mhz-66Mhz Core Clock, x2 processor A1/A3, Orion A1, 2x8Mb Dimm, 340Mb HDD. |
| 6.00.03 BETA checksum PN 123635SW |
12/12/95 3D00 |
The release notes for this BIOS are available. |
| 6-00-05 BETA CheckSum P/N 123707SW |
7/2/96 9400 |
Part number has been changed to reflect
4Mb binary image size. Internal change. Menuing logic corrected. BIOS update text was incorrect. This has now been resolved. The status of BIOS update was not indicated on 'System summary'. This has now been resolved. The 'Cache menu' in advanced setup has been removed. Power management options in setup did not accurately represent facilities available. This has now been resolved. Co-processor type reporting in 'System summary' has been disabled. ECP DMA is now configured. Certain setup features are now dependant upon the revision level of processor and Orion silicon. SIO timeout only supported units of minutes. This has now been resolved. SMI timer fail and BIOS virus detection were using same CMOS locations. This has now been resolved. Help messages were being displayed incorrectly. This has now been resolved. Internal change. Support for multiple processor stepping levels required multiple BIOS update patches. This has now been resolved. If the processor ID was not recognised the date string in signon would be blank. This has now been resolved. Internal change. All device numbers for PCI devices are now made available in the setup segment. Support for P6 stepping level C0 has been included. The BIOS memory test now extends to 4Mb rather than 64K. Warm boot sometimes would hang machine. This has now been fixed. The memory test algorithm has been improved. IPR 1466 - CD-ROM mode reported incorrectly. Now fixed. IPSL safe configuration showed incorrect cache type. Now resolved. IPSL safe configuration showed IOQ depth as 1 for everything upto OPB A2 silicon. Now shows depth as 8, for silicon upto OPB B0. IPR 1224 - ISA legacy resources above 1Mb were being reflected at 8Mb boundary. This has now been resolved. Redundant initialisation of DRAM row limits no longer takes place. SMM now works on Orion B0 silicon. |
| 6.00.06 BETA CheckSUM |
4/3/96 9F00 |
Occasionally, machines would hang on
re-boot, with a message stating 'stack overflow ... system halted'. This has now been
resolved. IPR 2027 - Power saving mode for IDE hard drives did not work. This has been fixed. No beep code would be reported if DIMMs not fitted. This has now been resolved. First boot after clearing CMOS does not work. This has been resolved. IDE hard disk standby mode was being greyed out if chipset silicon revision did not support SMI handling. This has now been resolved. IPR 1933 - PCI Lan card causes NT to lock up. This has now been resolved. LS security card (Diva) PnP option ROM was not being executed. This has now been resolved. Adaptec 2940 cards failing during boot. This has now been resolved. Standby SMIs were causing machine hangs. This has now been resolved. Setup option for PCI error handling were not visible. This has now been resolved. Setup option for 'Disk 3' was showing 'maximum performance' mode, even if no drive was connected. This has been resolved. Power management was not working with Windows NT. This has been resolved. ECC for memory was disabled. This has now been resolved. |
| 6.00.07 BETA CheckSUM |
14/3/96 9700 |
The cache size was not being correctly
reported on 512K versions. This has been resolved. Memory ECC was only being correctly generated for 64 bit writes. This has now been resolved. During investigation of Orion A2 silicon it was noticed that the OPB latency timer was not being set correctly. This has been corrected. During investigation of Orion A2 silicon it was noticed that a couple of registers were not being initialised. This has been fixed. During investigation of Orion A2 silicon it was noticed that ECC single bit error correction for DRAM as being enabled. This has been corrected. During investigation of Orion A2 silicon it was noticed that the minimum chipset latency was too low. This has been corrected. 3D accelerated video card fails. This has been resolved. IPR 2033 - a fix has been provided to cure problems with restarting from an SMI during a HLT instruction. An issue with the IOQ depth setting has been resolved. |
| 6.00.08 BETA |
12/4/96 | The object of this release is to provide the latest firmware to the field. |
| 6.00.09 BETA CheckSUM |
15/4/96 7600 |
The BIOS signon copyright message has
been changed to 1996, instead of 1995. Adaptec 2940 configuration failed to boot MS-DOS 6.2/V. This was caused by I/O port corruption at 1160 to 1163 causing the PCI card to fail. This has now been resolved. Adaptec 2940 option ROM caused ‘F1’ for ROM SETUP to fail. This has now been resolved. |
| 6.00 RELEASE checksum PN 123707SW |
29/4/96 7600 |
This release is functionally unchanged from the previous BETA 6.00.09 version. |
