| Release |
Date |
Changes |
| Discovery
BIOS release |
8.00.02
Beta
Checksum
P/N 157550SW |
26/4/96
4300 |
The object of this release is to provide
the latest software to the field.
013) \PLATFORM\DISCO\OEMCONF.INC JPU 10/04/96
Change BIOS_ENGNR_VERSION to 0FFh for engineering builds until the next release.
014) \PLATFORM\DISCO\OPTIONS.INC JPU 12/04/96
\PLATFORM\DISCO\PROCS.INC
\PLATFORM\DISCO\POSTTABL.ASM
\CHIPSETS\ORION\ORION.ASM |
| Problem |
As part of the error logging code there
is a need to enable the BERR# signal drivers in the PCI agents, to do this a reset has to
be performed after setting up an OPB register. Also there are several erratas which are
fixed by changing the I/O queue depth to 1 which is set via the same reset mechanism. |
| Cause |
Code to set these options up has not yet
been placed into this project. |
| Cure |
Add a routine to be called early in POST
to reset the machine after programming up the OPB to drive the relevant configuration
lines during reset. |
| Note : |
This mod currently sets the config
register to 0280h as defined by the equate OPB_CONFIG_BITS in options.inc. This will
enable the BERR# driver and select an I/O queue depth of 1. Also this mod is controled by
a switch called EN_OPB_RESET_CONFIG which is currently set to TRUE by this mod and should
be uncommented in options.inc to disable.
015) \CHIPSETS\ORION\ORION.INC JPU 19/04/96 |
| Problem |
Some of the chipset equates in this
chipset file are incorrect. |
| Cause |
Thats just how it is .... |
| Cure |
Correct the offending bits which are to
be used by the error logging SMI code, hence how they were discovered ....
016) \CORE\SPSETUP.ASM JPU 20/04/96 |
| Problem |
The 'Press F1 For Setup' and 'ESC For
Fast POST' messages do not currently get produced. |
| Cause |
Mod 009 moved the setup code and data
into a different ROM page and the MRI text strings are also contained in that same area of
the ROM so when decompressing the MRI strings the wrong page of the ROM is visible. |
| Cure |
Add ROM page selection code around the
decompression of the MRI strings as for the setup code and data ... |
| Note : |
This mod is controlled via the same
switch (ALT_SETUP_SEG) as mod 009 as it should have been done at the same time.
017) \OPTIONS\SMP\SMP.ASM SHM 20/04/96 |
| Problem |
The Level two cache size for each of the
processors present is not placed into the MP tablev as required to provide information for
the SMIC inventory collecting. |
| Cause |
No fields dedicated to this function in
the MP table. |
| Cure |
Added code to the MP table setup which
builds an OEM option table. The code sets up this table which is filled after each of the
availabe processors is interegated. |
| Note : |
An intermediate step was required to
save this information in readable RAM when each processor was run. This data is then
copied into the OEM table.
018) \PLATFORM\DISCO\OPTIONS.INC JPU 23/04/96
\CORE\MEMORYLI.ASM
\CORE\MEMORYLI.TXT
\CHIPSETS\ORION\ORION.ASM |
| Problem |
The machine reports the memory type as
being non-parity which is actually correct but that is because the DIMM's are ECC and it
should be changed to reflect this information. |
| Cause |
The CMOS is read by setup etc... but it
was never actually written to a correct value it was only ever defaulted and when it was
originally written it wasn't ECC aware. |
| Cure |
Add code in the memory sizing routine to
set up the CMOS location for memory type correctly depending upon the type of DIMM's found
and update setup code to print the correct text message depending upon the state of that
CMOS location. |
| Note : |
This mod is controlled via a switch
called ECC_DETECT_DIMM which is currently set to TRUE by this mod.
019) \CHIPSETS\ORION\ORION.ASM JPU 23/04/96
\PLATFORM\DISCO\OPTIONS.INC
\PLATFORM\DISCO\POSTTABL.ASM |
| Problem |
We know when ECC DIMM's are fitted due
to the previous mod but ECC initialization and correction is not currently performed. |
| Cause |
Wasn't possible until the previous
detection was performed. |
| Cure |
Add code to force correct ECC bits in
whole of memory during POST and to enable the ECC correction function within the memory
controller whenever ECC DIMM's are present. |
| Note : |
This mod is controlled via a switch
called FIX_ECC_IN_POST which is currently set to TRUE by this mod.
020) \OPTIONS\SMP\SMP.ASM SHM 24/04/96 |
| Problem |
Incorrect parameters passed to
CSET_Phase2setShadowAttrib |
| Cause |
Required attributes not being saved. |
| Cure |
Now save required attributes and recall
them when required.
021) \OPTIONS\SMP\SMP.ASM JPU 24/04/96 |
| Problem |
When the CMOS is cleared down the
machine takes minutes to complete the last stage of POST. It ends up with a port 80 code
of 0D3h which is an output from the cache config routine. |
| Cause |
The port 80 was a red herring as it was
the last code output but the error didn't lie within the cache code it happened upon
return to the InitMPStructures code. When the CMOS is corrupt a processor count of 0 is
used as a default and then when starting up the application processors this count is used
but it is decremented before it is tested (.repeat;dec value; until value == 0) hence it
thought it had to start up 255 application processors and this takes a long time. This
will also occur when CMOS is good but the user selects to have 0 application processors
started up. |
| Cure |
Change the loop control logic to use a
.while !(value==0); dec value;.endw so that if the value is 0 initially it will handle it
correctly. |
| Note : |
This mod is controlled via a switch
called MPLOOP_BADCMOS_FIX which is currently set to TRUE by this mod.
022) \PLATFORM\DISCO\PROCS.INC JPU 24/04/96 |
| Problem |
In mod 019 above this file was also
modified and should have been booked in otherwise build errors occur. |
| Cause |
Oversight when booking in mod. |
| Cure |
Book in the new file to correct the
build error. There is an externdef in this file for a routine used by the mod 019 and and
error is produced indiacting it cannot locate the routine.
023) \PLATFORM\DISCO\POSTTABL.ASM SHM 24/04/96
\PLATFORM\DISCO\DISCOVER.ASM |
| Problem |
CPU data for SMIC BIOS page 2 not being
placed in MP table. |
| Cause |
SMIC BIOS option ROM being called before
the MP initialisation code. |
| Cure |
BIOS updated to call the SMIC BIOS page2
code after MP initialisation. |
| Note : |
This mod is placed in here to allow FPSC
testing, this may be removed when the full version of the SMIC BIOS is released which
contains the user binary and other pages.
024) \PLATFORM\DISCO\OEMCONF.INC JPU 24/04/96
Change signon version number to make an internal tracable release.
Version information set to 8.00.02.
025) \PLATFORM\DISCO\APRTIME.INC JPU 24/04/96
Book in to allow a tracable release to be built if required :
AprBuildTime EQU "16:12:48" ; Current Time string
AprBuildDate EQU "24th April 1996" ; Current Date String
026)IMAGE.BIN JPU 24/04/96
Tracable internal release of Discovery BIOS V8.00.02 :
File: image.bin 24-04-1996 16:16:32 262144 bytes Checksum 4300
Discovery BIOS Version 08.00.02 24th April 1996 16:12:48
Copyright (C) 1985-1996 Apricot Computers Ltd. |
8.00.03
Beta
checksum
PN 157550SW |
8/7/96
9800 |
File Information
File: 80003.bin
Known Problems / Limitations
Netware / Unixware SMP do not currently work although Windows NT MP & Netware BETA
(Green River) do work.
There is a CMOS corruption problem when power cycling a machine we do not yet know if this
is a Hardware / BIOS issue and it is currently under investigation.
Problem with use of 2940W cards have been seen with various OS installs however with the
use of 2940UW cards the problems all disappear.
The SMIC card MUST currently be placed at C800 (as suggested in the SMIC BIOS release
notes for 2.00.02) and will not work correctly at D000h.
IPR’s 2283 (Novell V35+ Card) & 2285 (Digiboard) have not been fixed 100% but is
was found that these cards require a whole 64K segment to themselves and with the onboard
adaptec’s and the SMIC option rom space is limited before we even add adapter cards,
however these cards will work at 0A000h address range which is where the graphics video
ram should be, but because these cards are for use under Netware which doesn’t use
graphics mode it is possible to run them there for the time being to facilitate testing at
this stage.
After an EISA CMOS clear the onboard adaptecs are disabled and it is necessary to run the
ECU to enable them. (This was intended to be fixed but still seems to be faulty).
IPR 2246 - Cannot recreate this please retest.
IPR 2248 - Doesn’t stop system working and we will look into it soon (lower
priority).
Password issues (IPR’s 2292 à 2295) these need discussing / documenting as the code
is doing exactly what we expect it to and if it should behave in a different way then
discuss it and let us know.
IPR 2330 - The ECU comes from MCS and it has an automatic allocation algorithm build into
it and if things are placed on the same IRQ it will shuffle everything around to resolve
any resource conflicts so we have no control over this but with a small amount of playing
around it is possible to configure things exactly as you want them, or failing this the
automatic checking / config option can be turned off allowing manual configuration.
IPR 2382 - This fails on a particular machine and works on the machine in the BIOS group
and it was retested on another machine which also worked so we suspect a faulty test
machine.
NOTE : There are mods in this BIOS which require the hardware to be of the latest build
standard please ensure that the hardware you are using is to the latest revision otherwise
any results will be unreliable.
Reprogramming the BIOS
Using JFLASH.EXE the following command line should be used :
JFLASH -F:80003.BIN -O:40000 -W<CR>. |
8.00.04
Beta
checksum
PN 157550SW |
15/7/96
5E00 |
File Information
File: 80004.bin 12-07-1996 14:33:56 262144 bytes
Discovery BIOS Version 08.00.04 12th July 1996 14:29:46
Copyright (C) 1985-1996 Apricot Computers Ltd.
Known Problems / Limitations
There is a CMOS corruption problem when power cycling a machine we do not yet know if this
is a Hardware / BIOS issue and it is currently under investigation.
Problem with use of 2940W cards have been seen with various OS installs however with the
use of 2940UW cards the problems all disappear.
The SMIC card MUST currently be placed at C800 (as suggested in the SMIC BIOS release
notes for 2.00.02) and will not work correctly at D000h.
IPR’s 2283 (Novell V35+ Card) & 2285 (Digiboard) have not been fixed 100% but is
was found that these cards require a whole 64K segment to themselves and with the onboard
adaptec’s and the SMIC option rom space is limited before we even add adapter cards,
however these cards will work at 0A000h address range which is where the graphics video
ram should be, but because these cards are for use under Netware which doesn’t use
graphics mode it is possible to run them there for the time being to facilitate testing at
this stage.
After an EISA CMOS clear the onboard adaptecs are disabled and it is necessary to run the
ECU to enable them. (This was intended to be fixed but still seems to be faulty).
IPR 2246 - Cannot recreate this please retest.
IPR 2248 - Doesn’t stop system working and we will look into it soon (lower
priority).
Password issues (IPR’s 2292 à 2295) these need discussing / documenting as the code
is doing exactly what we expect it to and if it should behave in a different way then
discuss it and let us know.
IPR 2330 - The ECU comes from MCS and it has an automatic allocation algorithm build into
it and if things are placed on the same IRQ it will shuffle everything around to resolve
any resource conflicts so we have no control over this but with a small amount of playing
around it is possible to configure things exactly as you want them, or failing this the
automatic checking / config option can be turned off allowing manual configuration.
IPR 2382 - This fails on a particular machine and works on the machine in the BIOS group
and it was retested on another machine which also worked so we suspect a faulty test
machine.
Changes From Previous Version
Netware SMP and Unixware MP should now work.
It is possible to fit 2x2940W’s to the system when the SMIC is installed however we
still have a problem with 2940UW’s where only 1 can be fitted at present. This is
suspected to be due to a larger option ROM size on the 2940UW’s and is currently
under investigation.
Reprogramming the BIOS
Using JFLASH.EXE the following command line should be used :
JFLASH -F:80004.BIN -O:40000 -W<CR>. |
8.00.06
Beta
checksum
PN 157550SW |
15/8/96
3500 |
Known Problems / Limitations
IPR 2309 Problem with use of 2940W cards have been seen with various
OS installs however with the use of 2940UW cards the problems all disappear.
IPR’s 2283 (Novell V35+ Card) & 2285 (Digiboard) have not been fixed 100% but is
was found that these cards require a whole 64K segment to themselves and with the onboard
adaptec’s and the SMIC option rom space is limited before we even add adapter cards,
however these cards will work at 0A000h address range which is where the graphics video
ram should be, but because these cards are for use under Netware which doesn’t use
graphics mode it is possible to run them there for the time being to facilitate testing at
this stage.
IPR 2349 POST reports incorrect CPU cache size. This occurs very rarely (I have never
personally seen it in all the times I have turned on a Discovery) however Simon did see it
once when he was developing that code and the P6 actually returned the incorrect cache
size to him … ? (possible P6 bug ?)
Problem with enabling of error logging code when no SMIC card is fitted.
Also if error logging is enabled with a SMIC present then the system will boot but if
JFLASH is run or the ECU the system will hang with the FP LCD codes flickering between
several codes.
For best results this version of the BIOS should be used with V0.02 of the ECU which will
be available shortly however V0.01 will work fine in the mean time.
Changes From Previous Version
Date format changed in F1 setup to be UK ie. DD/MM/YY.
Fix for IPR 2414 - Administrator password requested to enter setup.
Fix for IPR 2416 - Clear screen between inputs if password entered more than once.
Change the system error logging menu so that it is not visible when entering setup in user
mode.
Remove floppy B: line from the setup menus as it is not possible to fit a 2nd floppy
drive.
Fix IPR 2506 - System is 1.4 MPS table compliant however one of the table version numbers
was incorrect and was still indicating MPS version 1.1.
Fix IPR 2429 - Discovery will now boot from a bootable CD-ROM using the onboard adaptec
7850.
Add some INCA clock chipset programming as requested by the hardware engineers as part of
a mod to fix the power cycling problem previously observed on the Rev C motherboards.
Reprogramming the BIOS
Using JFLASH.EXE the following command line should be used :
JFLASH -F:80006.BIN -O:40000 -W<CR>. |
8.00.07
Beta
checksum
PN 157550SW. |
3/9/96
8700 |
This BIOS has been tested in a machine
with 2x2940,1xSMIC and 4xProcs. In short it contains a new user binary which
shouldn’t crash now when enabling the error logging features, support for reporting
the BIOS version to the SMA, a fix for running the keyboard controller at the correct
speed to fix the power cycle problems with Rev C, a fix for the IRQ programming for the
parallel port, an increased boot fail counter threshold to simplify configuration during
production & SMA processor enable / disable support.
File Information
File: 80007.bin 03-09-1996 08:31:58 262144 bytes Checksum 8700
Discovery BIOS Version 08.00.07 3rd September 1996 08:30:28
Copyright (C) 1985-1996 Apricot Computers Ltd.
Known Problems / Limitations
Still investigating the 4 processor Windows NT problem, however this is now looking like a
BIOS issue as if it is tried with 8.00.04 it does work ?. I will be trying to narrow this
down to which later mod has caused this to start failing, hopefully in time for the next
release.
This BIOS has changes to the CMOS and will require a new ECU to work correctly, I will be
working on getting that ECU release out as soon as possible (3rd / 4th September).
Please refer to Discovery BIOS Limitations document for latest information.
Changes From Previous Version
Fixed user binary to stop the hang when enabling the error logging feature.
BIOS version now correctly reported for the SMA to pick up.
Fix for keyboard controller failure when power cycling for 2+ days.
IRQ 5/7 selection for parallel port should now work correctly.
Boot fail counter threshold moved to 6 from 3 to aid the factory when building and
configuring Discovery systems.
SMA processor Enable / Disable support.
Reprogramming the BIOS
Using JFLASH.EXE the following command line should be used :
JFLASH -F:80007.BIN -O:40000 -W<CR>. |
8.00.08
Beta
checksum
PN 157550SW. |
9/9/96
D700 |
This BIOS has been tested in a machine
with 2x2940,1xSMIC and 4xProcs. In short it contains a new user binary which should allow
an XXPRESS SMIC to be plugged into a Discovery without POST hanging, Fix for caching of
memory above 128MB which is what causes SCO UNIX to install slowly in a system with 192MB,
various small modifications to sort out the processor enable/disable via the SMA, Fix for
floppy problems when using Mitsubishi drives, MP table version placed on a switch as this
seems to have a bearing on Windows NT systems running with 4 processors (It works when the
MP table is 1.1?) and a warning string has been changed as it reflected incorrect
information.
File Information
File: 80008.bin 09-09-1996 14:09:30 262144 bytes Checksum D700
Discovery BIOS Version 08.00.08 9th September 1996 14:07:59
Copyright (C) 1985-1996 Apricot Computers Ltd.
Known Problems / Limitations
This BIOS has changes to the CMOS and will require a new ECU to work correctly, I will be
working on getting that ECU release out as soon as possible, I am currently talking to IBM
and MCS on this issue as I suspect it is a fundamental ECU issue and not necessarily a
problem with the code we have added ourselves. Please refer to Discovery BIOS Limitations
document for latest information.
Changes From Previous Version
Fixed user binary to allow use of XXPRESS SMIC without hanging POST.
Caching of >128MB memory now works (SCO slow install problem).
various small fixes to CMOS usage for SMA processor enable/disable code.
Floppy fix for Mitsubishi drives.
MP table version number now selectable via setup.
Warning text string updated for accuracy reasons.
Reprogramming the BIOS
Using JFLASH.EXE the following command line should be used :
JFLASH -F:80008.BIN -O:40000 -W<CR>. |
8.00.09
Beta
checksum
PN 157550SW. |
12/9/96
3E00 |
This BIOS has been tested in a machine
with 2x2940,1xSMIC and 4xProcs. In short it contains a fix to allow console redirection
within the SMA to work & a safeguard which ensures error logging functionality is
disabled if CMOS is corrupt.
File Information
File: image.bin 11-09-1996 17:07:56 262144 bytes Checksum 3E00
Discovery BIOS Version 08.00.09 11th September 1996 17:06:16
Copyright (C) 1985-1996 Apricot Computers Ltd.
Known Problems / Limitations
This BIOS requires Release 0.03 of the ECU to configure it, this ECU still has some
problems which I am currently talking to IBM and MCS who provide the ECU to us for
modification. Please refer to Discovery BIOS Limitations document for latest information.
Changes From Previous Version
Mod to fix console redirection from within the SMA.
Mod to ensure CMOS defaults when CMOS corrupt for enabling error logging features.
Reprogramming the BIOS
Using JFLASH.EXE the following command line should be used :
JFLASH -F:80009.BIN -O:40000 -W<CR>. |
8.00.10
Beta
checksum
PN 157550SW. |
17/9/96
2A00 |
Known Problems / Limitations
This BIOS requires Release 0.04 of the ECU to configure it, this ECU will be available
tomorrow. Please refer to Discovery BIOS Limitations document for latest information.
Changes From Previous Version
Mod to fix problem when error logging is enabled and the ECU / Jflash is run which
currently causes the system to grind to a halt with SMI’s.
Mod to change error logging defaults to Enabled.
Mod to change MP version default to V1.4.
Reprogramming the BIOS
Using JFLASH.EXE the following command line should be used :
JFLASH -F:80010.BIN -O:40000 -W<CR>. |
8.00.11
Beta
checksum
PN 157550SW. |
19/9/96
2300 |
This BIOS has been tested in a machine
with 2xProcs (200MHz 512K) running CCTEST under Windows NT Beta 4.0 MP. In short it
contains a fix to allow the machine to work with >200MHz processors which was
previously causing problems when booting / running Windows NT MP.
Known Problems / Limitations
This BIOS requires Release 0.04 of the ECU to configure it, this ECU is available on the
BIOS group web page. Please refer to Discovery BIOS Limitations document for latest
information.
NOTE : This BIOS has a problem with the error logging features which is currently under
investigation and ALL error logging should be DISABLED as they currently default to
ENABLED.
Changes From Previous Version
Change to ‘Safe’ chipset programming as provided by IPSL some time ago. The
change sets the I/O queue depth to 1 as opposed to 8 as there are chipset errata with it
set to 8 even though this was required as part of Intels ‘Safe’ chipset
programming values?.
Reprogramming the BIOS
Using JFLASH.EXE the following command line should be used :
JFLASH -F:80011.BIN -O:40000 -W<CR>. |
8.00.12
Beta
checksum
PN 157550SW. |
25/9/96
8000 |
File Information
File: 80012.bin 23-09-1996 10:46:06 262144 bytes Checksum 8000
Discovery BIOS Version 08.00.12 23rd September 1996 10:44:10
Copyright (C) 1985-1996 Apricot Computers Ltd.
Known Problems / Limitations
This BIOS requires Release 0.04 of the ECU to configure it, this ECU is available on the
BIOS group web page. Please refer to Discovery BIOS Limitations document for latest
information.
Changes From Previous Version
Mod to fix problem with error logging being enabled causing the machine to hang or
operating systems to trap.
Mod to ensure that the BSP number swapping code in the BIOS doesn’t get confused when
the BSP actually comes up as processor 0.
Reprogramming the BIOS
Using JFLASH.EXE the following command line should be used :
JFLASH -F:80012.BIN -O:40000 -W<CR>. |
8.00.13
Beta
checksum
PN 157550SW. |
30/9/96
6500 |
This BIOS has been tested in a machine
with 2xProcs (200MHz 512K) running CCTEST under Windows NT Beta 4.0 MP. In short it
contains a fix for the warm boot problem (Cirrus video chip behaving strangely under reset
conditions), the VRM voltage monitoring thresholds have been changed as they were
previously set to tight & the SMI handler for error logging will only output the port
80h value when the error is fatal.
File Information
File: image.bin 30-09-1996 13:43:18 262144 bytes Checksum 6500
Discovery BIOS Version 08.00.13 30th September 1996 13:41:47
Copyright (C) 1985-1996 Apricot Computers Ltd.
Known Problems / Limitations
This BIOS requires Release 0.04 of the ECU to configure it, this ECU is available on the
BIOS group web page. Please refer to Discovery BIOS Limitations document for latest
information.
Changes From Previous Version
Mod to fix warm boot crash. This involves a mod to wait for the Cirrus video to be
performing its vertical blanking before issuing the reset.
Change to implement wider ranges for the VRM voltage monitoring.
Change error logging SMI handler to increase its stack size as a safety measure and to
only output the port 80h debug value when a fatal error is detected. Please refer to
Discovery documentation for error log definitions and Fatal/Non-Fatal errors.
Reprogramming the BIOS
Using JFLASH.EXE the following command line should be used :
JFLASH -F:80013.BIN -O:40000 -W<CR>. |
8.00.14
Beta
checksum
PN 157550SW. |
3/10/96
6600 |
This BIOS has been tested in a machine
with 2xProcs (200MHz 512K), 1x2940 & 1x592 running Winthrax under Windows NT V3.51MP.
In short it contains a fix for the 3COM 592 EISA network card when Bus error logging is
enabled.
File Information
File: image.bin 03-10-1996 08:17:22 262144 bytes Checksum 6600
Discovery BIOS Version 08.00.14 3rd October 1996 08:15:52
Copyright (C) 1985-1996 Apricot Computers Ltd.
Known Problems / Limitations
This BIOS requires Release 0.04 of the ECU to configure it, this ECU is available on the
BIOS group web page. Please refer to Discovery BIOS Limitations document for latest
information.
Changes From Previous Version
Workaround for the 3COM 592 EISA network card under Windows NT & Netware. The 3COM
card generates EISA Bus Timeout errors which result in the EISA bus being reset and thus
loss of various peripherals which are on the ISA bus Eg. Floppy / Serial and RTC ….
Reprogramming the BIOS
Using JFLASH.EXE the following command line should be used :
JFLASH -F:80014.BIN -O:40000 -W<CR>. |
8.00
Release
checksum
PN 157550SW. |
7/10/96
3200 |
File Information
File: image.bin 03-10-1996 15:18:30 262144 bytes Checksum 3200
Discovery BIOS Version 08.00.00 3rd October 1996 15:16:58
Copyright (C) 1985-1996 Apricot Computers Ltd.
Known Problems / Limitations
This BIOS requires Release 1.00 of the ECU to configure it, this ECU is available on the
BIOS group web page. Please refer to Discovery BIOS Limitations document for latest
information.
Changes From Previous Version
Version number changed for factory release.
Reprogramming the BIOS
Using JFLASH.EXE the following command line should be used :
JFLASH -F:800.BIN -O:40000 -W<CR>. |
8.01.01
Beta
checksum
PN 157550SW |
9/1/97
2E00 |
Known Problems / Limitations
This BIOS requires Release 1.00 of the ECU to configure it, this ECU is available on the
BIOS group web page. Please refer to Discovery BIOS Limitations document for latest
information.
Changes From Previous Version
Change signon to be "FT4200" rather than "Discovery".
Fixed a bug highlighted during testing of next version of ECU (not yet released) where the
Adaptec Chips could never be enabled.
Fixed a bug highlighted during testing of Win95 OSR2 where CMOS was corrupted by its
Enhanced Plug and Play Configure during BOOT (caused problems next Boot!).
Added support for Processor Stepping Data for P6s B1 stepping (And removed P6 C0 support
to make room).
Reprogramming the BIOS
Using JFLASH.EXE the following command line should be used :
JFLASH -F:80101.BIN -O:40000 -W<CR>. |
Release 8.01
checksum
PN 157550SW |
30/01/97
5000 |
Known Problems / Limitations
This BIOS requires Release 1.00 of the ECU to configure it.
Changes From Previous Version
Version number changed for factory release.
Reprogramming the BIOS
Using JFLASH.EXE the following command line should be used :
JFLASH -F:801.BIN -O:40000 -W<CR>. |
8.02.01
Beta
checksum
PN 157550SW |
13/03/97
1C00 |
Changes From Previous Version
Fixed PRF 01780 - 8x64MB Dimms in Discovery. NT will not communicate with the floppy
drive.
Fixed IPR 03202 - FT4200 2Gb system only counts to 32Mb RAM.
Known Problems / Limitations
This BIOS requires Release 1.00 of the ECU to configure it.
Reprogramming the BIOS
Preferred method: Use recovery disk.
Alternate method: Using JFLASH.EXE the following command line should be used :
JFLASH -F:80101.BIN -O:40000 -W<CR>.
Testing done by BIOS Group
Test Board Software Result
1 HB84769 SN602112, 4x256Mb BIOS Memory Test Pass (1Gb found)
2 HB84769 SN602112, 4x256Mb TES640 DMA Test Pass
3 HB84769 SN602112, 4x256Mb WinNT Pass (Boots and shows 1Gb)
4 HB84769 SN602112, 2x256Mb BIOS Memory Test Pass (512Mb found)
5 HB84769 SN602112, 2x256Mb TES640 DMA Test Pass
6 HB84769 SN602112, 2x256Mb WinNT Pass (Boots and shows 512Mb)
7 HB84769 SN602112, 1x32Mb Dos, Norton SI Pass (Normal Speed)
8 HB84769 SN602112, 1x32Mb Visual Observation and What.EXE on Binary Pass (Signon Version
and What String Correct)
9 HB84769 SN602112, 1x32Mb WinNT4.0 Pass (Boots) |
8.02.02
Beta
checksum
PN 157550SW |
25/04/97
2A00 |
Changes From Previous Version
Fixed IPR 03164 - Discovery will not boot with 8x128MB DIMMs.
Fixed IPR 03202 - Discovery will not boot with 8x256MB DIMMs.
Known Problems / Limitations
The front panel displays the flashing error code 222F when booting with 8x256MB DIMMs.
NT hangs soon after booting with 8x256MB DIMMs installed.
Reprogramming the BIOS
Using JFLASH.EXE the following command line should be used :
JFLASH -F:80202.BIN -O:40000 -W<CR>.
Testing done by BIOS Group
All testing performed on HB84769/SN602112
| Test |
DRAM configuration |
Software |
Result |
| 1 |
256MB in slot 2 |
BIOS Memory Test
Boot MSDOS 6.22
Boot NT Server 3.51 |
Pass
(Boots and 256MB found) |
| 2 |
256MB in slots 2,4 |
BIOS Memory Test
Boot MSDOS 6.22
Boot NT Server 3.51 |
Pass
(Boots and 512MB found) |
| 3 |
256MB in slots 2,4,6,8 |
BIOS Memory Test
Boot MSDOS 6.22
Boot NT Server 3.51 |
Pass
(Boots and 1GB found) |
| 4 |
256MB in all 8 slots |
BIOS Memory Test
Boot MSDOS 6.22
Boot NT Server 3.51 |
Pass
(Boots and 2GB found). NT hangs later. |
| 5 |
128MB in slot 2 |
BIOS Memory Test
Boot MSDOS 6.22 |
Pass
(Boots and 128MB found) |
| 6 |
128MB in slots 2,4 |
BIOS Memory Test
Boot MSDOS 6.22 |
Pass
(Boots and 256MB found) |
| 7 |
128MB in slots 2,4,6,8 |
BIOS Memory Test
Boot MSDOS 6.22 |
Pass
(Boots and 512MB found) |
| 8 |
128MB in all 8 slots |
BIOS Memory Test
Boot MSDOS 6.22 |
Pass
(Boots and 1GB found). |
| 9 |
64MB in slots 2,4,6,8 |
BIOS Memory Test
Boot MSDOS 6.22
Boot NT Server 3.51 |
Pass
(Boots and 256 MB found). |
| 10 |
64MB in slots 2,4,6,8 |
Visual Observation and WHAT.EXE on Binary |
Pass
(Sign-on Version and What String Correct) |
|
8.02.03
Beta
checksum
PN 157550SW |
22/05/97
9700 |
Changes From Previous Version
Fixed NT hang with 2Gb of RAM.
Fixed boot failure with different DIMM sizes in banks 1 and 2.
Known Problems / Limitations
Possible reduction in performance when mixing different sized double-sided DIMMs or using
single sided DIMMs.
Reprogramming the BIOS
Using JFLASH.EXE the following command line should be used :
JFLASH -F:80203.BIN -O:40000 -W<CR>.
Testing done by BIOS Group
All testing performed on HB84769/SN602112
| Test |
DRAM configuration |
Software |
Result |
| 1 |
64MB in slot 2 |
Boot MSDOS 6.22 |
Pass
(Boots and 64MB found) |
| 2 |
64MB in slots 1,2 |
Boot MSDOS 6.22 |
Pass
(Boots and 128MB found) |
| 3 |
256MB in slots 1
64MB in slot 2 |
Boot MSDOS 6.22 |
Pass
(Boots and 320MB found) |
| 4 |
256MB in slots 1,3,5,7
64MB in slots 2,4,6,8 |
Boot MSDOS 6.22 |
Pass
(Boots and 1.25GB found). |
| 5 |
64MB in slots 1,3,5,7
256MB in slots 2,4,6,8 |
Boot MSDOS 6.22 |
Pass
(Boots and 1.25GB found) |
| 6 |
32MB in slot 2
64MB in slot 1 |
Boot MSDOS 6.22 |
Pass
(Boots and 96MB found) |
| 7 |
256MB in slots 3,4 |
Boot MSDOS 6.22 |
Pass
(Boots and 512MB found) |
| 8 |
256MB in all 8 slots |
Boot MSDOS 6.22
Boot NT Server 4.11
Run NT Explorer |
Pass
(Boots, 1GB found and NT Explorer runs) |
| 9 |
64MB in slot 2 |
Visual Observation and WHAT.EXE on Binary |
Pass
(Sign-on Version and What String Correct) |
|
8.02
Release
checksum
PN 157550SW |
19/06/97
A100 |
Known Problems / Limitations
Memory timings taken from DIMMs fitted in first bank and assumed to be the same for the
second bank.
Possible reduction in performance when mixing different sized double-sided DIMMs or using
single sided DIMMs.
Changes From Previous Version (8.01)
Problems with 128MB and 256MB DIMMs fixed (PRF 01780, IPR 03202, IPR 03164, IPR 03637 and
IPR 03638)
Version number changed for factory release.
Reprogramming the BIOS
Using JFLASH.EXE the following command line should be used :
JFLASH -F:802.BIN -O:40000 -W<CR>. |
8.03.01
Beta
checksum
PN 157550SW |
19/08/97
6200 |
Changes From Previous Version
Master Latency Timer reduced to 72 clocks.
Fixed IPR 03969. Cache size now correctly reported for processors with 1MB L2 cache.
Fixed PRF 001956. Intel Pro 100B Network card can now be installed under NT
Known Problems / Limitations
None.
Reprogramming the BIOS
Using JFLASH.EXE the following command line should be used :
JFLASH -F:80301.BIN -O:40000 -W<CR>.
Testing done by BIOS Group
| Test |
Configuration |
Test Procedure |
Result |
| 1 |
HB84769/SN602112
MS-DOS 6.22
PCI.EXE 2.2 |
Boot MSDOS 6.22 and check bit settings of
Master Latency Timer register with PCI.EXE 2.2 |
Pass |
| 2 |
HA81904, S/N 442547 with 4 processors with 1MB
L2 cache. |
Boot machine and note cache size reported by
POST |
Pass
Cache size displayed as 1M |
| 3 |
HA81904, S/N 442547 with 4 processors with
512K L2 cache. |
Boot machine and note cache size reported by
POST |
Pass
Cache size displayed as 512K |
| 4 |
HA81904, S/N 442547
Intel Pro 100B network card
MS-DOS 6.22
PCI.EXE 2.2 |
Boot MSDOS and check that memory space for
card is enabled using PCI.EXE |
Pass |
| 5 |
HA81904, S/N 442547
Intel Pro 100B network card
NT Server 4 |
Boot NT and add card and driver. Check network
can be accessed via this card. |
Pass |
| 6 |
HB84769/SN602112
MS-DOS 6.22 |
Visual Observation and WHAT.EXE on Binary |
Pass
(Sign-on Version and What String Correct) |
|
8.03.02
Beta
checksum
PN 157550SW |
19/08/97
FA00 |
Changes From Previous Version
Fixed IPR 04064. Application processors disabled when AMI RAID card installed.
Fixed IPR 04112. Intel Pro 100B Network card now works in slot P2. (IPR 02978 may also be
fixed by this modification)
Fixed IPR 04105. Cache size now correctly displayed for 1M processors in setup screens.
Known Problems / Limitations
Interrupts for PCI cards installed in slots 4,5,6 may not work.
PCI cards which are installed without allocating an IRQ using the ECU may fail to obtain
an interrupt even though there are interrupt lines apparently available.
A PCI to PCI bridge may cause interrupts for devices on that bridge and all
higher-numbered bridges to fail
Reprogramming the BIOS
Using JFLASH.EXE the following command line should be used :
JFLASH -F:80302.BIN -O:40000 -W<CR>.
Testing done by BIOS Group
| Test |
Configuration |
Test Procedure |
Result |
| 1 |
HC854848/SN713388 with 4 processors |
Ensure that SMIC displays flash boot message
at end of POST |
Pass |
| 2 |
HC854848/SN713388 with 4 processors |
Boot machine and check no application
processors have been disabled |
Pass |
| 3 |
HA81904, S/N 442547 with single processor.
3C905 in slot 2
MSDOS 6.22
PCI.EXE V2.2
3C90XCFG.EXE V2.1 |
Allocate IRQ 11 to 3C905 with ECU. Use PCI.EXE
to check IRQ 11 allocated. Run 3C90XCFG.EXE interrupt test. |
Pass
|
| 4 |
HA81904, S/N 442547 with 1 processors with
1MByte L2 cache. |
Note cache size reported by System Summary and
Advanced/Cache control menu screens in Setup |
Pass
Cache size displayed as 1024k in both screens |
| 5 |
HA81904, S/N 442547 with 1 processors with
512KByte L2 cache. |
Note cache size reported by System Summary and
Advanced/Cache control menu screens in Setup |
Pass
Cache size displayed as 512k in both screens |
| 6 |
HA81904, S/N 442547
MS-DOS 6.22 |
Visual Observation and WHAT.EXE on Binary |
Pass
(Sign-on Version and What String Correct) |
|
8.03
Release
checksum
PN 157550SW |
03/09/97
D700 |
Known Problems / Limitations
Memory timings taken from DIMMs fitted in first bank and assumed to be the same for the
second bank.
Possible reduction in performance when mixing different sized double-sided DIMMs or using
single sided DIMMs.
Interrupts for PCI cards installed in slots 4,5,6 may not work.
PCI cards which are installed without allocating an IRQ using the ECU may fail to obtain
an interrupt even though there are interrupt lines apparently available.
A PCI to PCI bridge may cause interrupts for devices on that bridge and all
higher-numbered bridges to fail
Changes From Previous Version (8.02)
Fixed IPR 04064. Application processors not now disabled when AMI RAID card installed.
Fixed IPR 04112. Intel Pro 100B Network card now works in slot P2.
Fixed IPR 04105. Cache size now correctly displayed for 1M processors in setup screens.
Copyright end-date changed to 1997.
Version number changed for factory release.
Reprogramming the BIOS
Using JFLASH.EXE the following command line should be used :
JFLASH -F:803.BIN -O:40000 -W<CR>. |
| Discovery
SMIC BIOS |
2.00.01
Beta
Checksum
P/N 157770SW |
26/4/96
C000 |
The object of this release is to provide
the latest software to the field.
File Details
Length:16kB
Target Device utility AMD 29F010 (Apricot part # 12327230
Contents
Inventory reporting (CPU, L2 cache, Memory, EISA & PCI cards, Serial, Parallel, and
floppy)
Known omissions
SMIC pages 0, 1, 3, 4, 6, 7
Disable individual CPU’s not implemented
FP_PARALLELMODE always set to zero
Checking POST error log for DIMM errors not implemented
Setting up Additional error log information to indicate which DIMM and PCI failed
Additional Information
This BIOS must be used in conjunction with the Discovery BIOS version 8.00.02
Debug messages have been left on to aid in FPSC development
Known problems
MP table count and table length seem inconsistent
Testing
Not all combinations of PCI, EISA, CPU and DIMM’s have been tested.
Full SMI testing has not been completed. Various combinations have been tried to prove
basic flow. |
2.00.02
BETA
checksum
PN 157770SW. |
20/5/96
B000 |
Contents
SMICPG0: Dummy Option ROM
SMICPG1 : POST call sequencer and decision logic
SMICPG2 : Inventory reporting (CPU, L2 cache, Memory, EISA & PCI cards, Serial,
Parallel, and Floppy)
SMICPG3 : Console Redirection
SMICPG4
SMICPG5 : Miscellaneous FPSC - Variable setting
SMICPG6 : Self Test
SMICPG7 : Flash Disk
SMIC option ROM checking.
Known omissions
Updating of the Voltage Descriptor inside the SMI Handler. Due to a new variable being
defined on the day of release.
Checking of the error log for failed CPU’s not implemented until Fault Resilient
Booting completed. This may not be necessary depending on how the processors are disabled/
enabled.
FP_PARALLELMODE always set to zero
Additional information
This BIOS must be used in conjunction with the Discovery BIOS version 8.00.03
The SMIC needs to be executed in ROM Space at 0C800h so the jumper on board needs to be
set to the left hand position, when the board has the connector towards you.
If no Front Panel is connected, the SMIC will take 2 minutes before reporting the error.
If the message "SMIC option ROM conflict" appears, the jumper may be in the
incorrect setting.
The corresponding userbinary, has been copied to the Motherboard BIOS space and checked in
ready for the relevant BIOS release.
Known problems
The Flash Disk utility does not run correctly.
JFlash will not program the SMIC BIOS.
What -f strings
File: smic.bin 17-05-1996 16:20:44 131072 bytes |
2.00.04
Beta
checksum
PN 157770SW. |
29/8/96
3A00 |
Programming
Target device: AMD 29F010 (Apricot part # 12327230)
Contents
SMICPG0: Dummy Option ROM
SMICPG1 : POST call sequencer and decision logic
SMICPG2 : Inventory reporting (CPU, L2 cache, Memory, EISA & PCI cards, Serial,
Parallel, and Floppy)
SMICPG3 : Console Redirection
SMICPG4
SMICPG5 : Miscellaneous FPSC - Variable setting
SMICPG6 : Self Test
SMICPG7 : Flash Disk
IPR 2525 Fixed. The BIOS version reporting requires the motherboard BIOS 8_00_07 or
greater to be used inc onjunction with SMIC 2_00_04. Motherboard BIOS 8_00_07 is not yet
available.
IPR 2519, IPR 2517, IPR 2516 Fixed. PCI slot numbering now correct in the SMIC.
EISA and PCI LAN cards now supported - EISA 3C592, PCI 3C595
IPR 2518, FP_PARALLELMODE now implemented.
IPR 2518, The correct data is reported to the SMA
IPR 2523, SMIC is reporting processor types correctly.
Known omissions
Updating one of the Voltage Descriptor inside the SMI Handler.
Additional information
If no Front Panel is connected, the SMIC will take 2 minutes before reporting the error.
What -f strings
File: smic.bin 28-08-1996 16:35:46 131072 bytes
SMIC BIOS Version 2.00.04
Copyright © 1995-1996 Apricot Computers Ltd |
2.00.05
Beta
checksum
PN 157770SW. |
10/9/96
5D00 |
Programming
Target device: AMD 29F010 (Apricot part # 12327230)
Utility: jflash -smic -p:C8 -q -f:smic.bin
Contents
SMICPG0: Dummy Option ROM
SMICPG1 : POST call sequencer and decision logic
SMICPG2 : Inventory reporting (CPU, L2 cache, Memory, EISA & PCI cards, Serial,
Parallel, and Floppy)
SMICPG3 : Console Redirection
SMICPG4
SMICPG5 : Miscellaneous FPSC - Variable setting
SMICPG6 : Self Test
SMICPG7 : Flash Disk
The correct voltage Descriptors are now updated inside the SMI Handler.
IPR 2522 : Disabled processor now reported correctly.
IPR 2524 : Memory configuration now reported correctly.
IPR 2761 : Processor Voltages now reported correctly.
IPR 2564 : Processors can now be disabled by the SMA.
IPR 2518 : Parallel Port IRQ now reported correctly.
XXPRESS SMIC cards will not hang on Discovery board.
Additional information
The new SMIC release should be used with motherboard BIOS 8.00.08for full functionality.
If no Front Panel is connected, the SMIC will take 2 minutes before reporting the error.
Known problems
Console Re-direction hangs when requested from the SMA.
What -f strings
File: smic.bin 09-09-1996 14:39:02 131072 bytes
SMIC BIOS Version 2.00.05
Copyright © 1995-1996 Apricot Computers Ltd |
2.00.06
Beta
checksum
PN 157770SW. |
11/9/96
6700 |
Programming
Target device: AMD 29F010 (Apricot part # 12327230)
Utility: jflash -smic -p:C8 -q -f:smic.bin
Contents
SMICPG0: Dummy Option ROM
SMICPG1 : POST call sequencer and decision logic
SMICPG2 : Inventory reporting (CPU, L2 cache, Memory, EISA & PCI cards, Serial,
Parallel, and Floppy)
SMICPG3 : Console Redirection
SMICPG4
SMICPG5 : Miscellaneous FPSC - Variable setting
SMICPG6 : Self Test
SMICPG7 : Flash Disk
IPR 2559 : Pass through mode now works.
Support added for 3Com cards 900 and 905
Additional information
The new SMIC release should be used with motherboard BIOS 8.00.09 to work correctly.
If no Front Panel is connected, the SMIC will take 2 minutes before reporting the error.
What -f strings
File: smic.bin 11-09-1996 11:08:02 131072 bytes
SMIC BIOS Version 2.00.06
Copyright © 1995-1996 Apricot Computers Ltd |
2.00.07
Beta
checksum
PN 157770SW. |
30/9/96
6600 |
Programming
Target device: AMD 29F010 (Apricot part # 12327230)
Utility: jflash -smic -p:C8 -q -f:smic.bin
Contents
SMICPG0: Dummy Option ROM
SMICPG1 : POST call sequencer and decision logic
SMICPG2 : Inventory reporting (CPU, L2 cache, Memory, EISA & PCI cards, Serial,
Parallel, and Floppy)
SMICPG3 : Console Redirection
SMICPG4
SMICPG5 : Miscellaneous FPSC - Variable setting
SMICPG6 : Self Test
SMICPG7 : Flash Disk
SMI Error Logging problem fixed.
CPU Card detection now sets the tested bit in the descriptor which allows the SMA to
continue and display the CPU’s present on the card.
Additional information
The new SMIC release should be used with motherboard BIOS 8.00.09 or later to work
correctly.
If no Front Panel is connected, the SMIC will take 2 minutes before reporting the error.
What -f strings
File: smic.bin 11-09-1996 13:48:18 131072 bytes
SMIC BIOS Version 2.00.07
Copyright © 1995-1996 Apricot Computers Ltd |
2.00
Release
checksum
PN 158489SW. |
7/10/96
6500 |
Programming
Target device: AMD 29F010 (Apricot part # 12327230)
Utility: jflash -smic -p:C8 -q -f:smic.bin
Contents
SMICPG0: Dummy Option ROM
SMICPG1 : POST call sequencer and decision logic
SMICPG2 : Inventory reporting (CPU, L2 cache, Memory, EISA & PCI cards, Serial,
Parallel, and Floppy)
SMICPG3 : Console Redirection
SMICPG4
SMICPG5 : Miscellaneous FPSC - Variable setting
SMICPG6 : Self Test
SMICPG7 : Flash Disk
Additional information
The new SMIC release should be used with motherboard BIOS 8.00 to work correctly.
If no Front Panel is connected, the SMIC will take 2 minutes before reporting the error.
The Part Number has changed from 157770SW to 158489SW to align with the entry in the
MANMAN database.
What -f strings
File: smic.bin 04-10-1996 09:35:04 131072 bytes
SMIC BIOS Version 2.00
Copyright © 1995-1996 Apricot Computers Ltd |
| Discovery
/ Shogun FPSC firmware disk |
BETA 1A
PN 158022SW. |
17/6/96 |
This is the initial release of the
Discovery / Shogun Front Panel Systems
Controller (FPSC) firmware, version 4.013, and contains the following binaries, |
1.00
Release
PN 158022SW. |
9/10/96 |
Binary for EVEN address EPROM (IC3):
158020SW.BIN
Binary for ODD address EPROM (IC2): 158019SW.BIN
Binary for FLASH ROM (IC1): 158018SW.BIN
Known Bugs and Limitations
New voltage variables (shown below) were introduced for the Discovery project - the
associated threshold values for these variables are at present undefined:
SCMB1V5AVoltage
SCMB1V5BVoltage
SCDC3Voltage
SCMB3V3Voltage
MB3V3Voltage
MB1V5AVoltage
MB1V5BVoltage
DC3Voltage
MBCPU_1_Voltage
MBCPU_2_Voltage
CARDCPU_1_Voltage
CARDCPU_2_Voltage
SCMBCPU_1_Voltage
SCMBCPU_2_Voltage
SCCARDCPU_1_Voltage
SCCARDCPU_2_Voltage
File List
Volume in drive A is 158022SW
Volume Serial Number is 6C9D-54B9
Directory of A:\
10/08/96 02:10p 131,072 158020SW.BIN
10/08/96 02:12p 131,072 158019SW.BIN
10/08/96 02:10p 131,072 158021SW.BIN
3 File(s) 393,216 bytes
1,064,448 bytes free |
Beta 2A
PN 158022SW. |
28/11/96 |
Introduction
This is the third release of this product for the Discovery Server System.
Binary for EVEN address EPROM (IC3): 158020SW.BIN
Binary for ODD address EPROM (IC2): 158019SW.BIN
Binary for FLASH ROM (IC1): 158021SW.BIN
Changes Since Last Release
Incorporated fixes for IPR’s - see 0, and added threshold values for the following
variables:
SCMB1V5AVoltage
SCMB1V5BVoltage
SCDC3Voltage
SCMB3V3Voltage
MB3V3Voltage
MB1V5AVoltage
MB1V5BVoltage
DC3Voltage
MBCPU_1_Voltage
MBCPU_2_Voltage
CARDCPU_1_Voltage
CARDCPU_2_Voltage
SCMBCPU_1_Voltage
SCMBCPU_2_Voltage
SCCARDCPU_1_Voltage
SCCARDCPU_2_Voltage
PRF’s, IPR’s Fixed since last release
02704
02960
Known Bugs and Limitations
None.
File List
Disk #1 /1
Volume in drive A is 158022SW
Volume Serial Number is B4DA-E377
Directory of A:\
11/28/96 01:16p 131,072 158021SW.BIN
11/28/96 01:16p 131,072 158020SW.BIN
11/28/96 01:22p 131,072 158019SW.BIN
3 File(s) 393,216 bytes
1,064,448 bytes free |
Release 1
PN 159667SW |
30/01/97 |
Binary for EVEN address EPROM (IC3):
159669SW.BIN
Binary for ODD address EPROM (IC2): 159668SW.BIN
Binary for FLASH ROM (IC1): 159670SW.BIN
Changes Since Last Release
None.
PRF’s, IPR’s Fixed since last release
None.
Known Bugs and Limitations
As indicated in the Beta 1 release, also DVT tests have shown that is not possible to
flash upgrade a currently installed copy of the 4.114 firmware (IPR: 03142). |
2B
Beta
PN 159667SW |
11/02/97 |
This is the fourth release of this
product for the Discovery Server System.
Binary for EVEN address EPROM (IC3): 159669SW.BIN
Binary for ODD address EPROM (IC2): 159668SW.BIN
Binary for FLASH ROM (IC1): 159670SW.BIN
Changes Since Last Release
The firmware version numbering scheme has now been altered to identify beta releases, the
following convention is now used:
LCD Description
A System type i.e. Shogun = 3 or Discovery = 4
B PSU type i.e. Shogun = 0, or N+1 = 1
C Level of functionality.
D Beta = [a - f, and 9 - 1], or Release = 0
PRF’s, IPR’s Fixed since last release
Software solution to flashing LCD problem.
Modified access permissions for AC15Alatch and Latch15AAction.
Corrected monitoring of CircuitBreakerSense
Hardware modifications dictate new behaviour of LED indicators.
Known Bugs and Limitations
DVT tests have shown that is not possible to flash upgrade a currently installed copy of
the 4.114 firmware. Currently under review.
File List
Disk #1 /1
Volume in drive A is 159667SW
Volume Serial Number is 88FA-A7C1
Directory of A:\
11/02/97 10:24 131,072 159668SW.BIN
11/02/97 10:24 131,072 159669SW.BIN
11/02/97 10:24 131,072 159670SW.BIN
3 File(s) 393,216 bytes
1,064,448 bytes free |
2
Release
PN 159667SW |
18/02/97 |
Binary for EVEN address EPROM (IC3):
159669SW.BIN
Binary for ODD address EPROM (IC2): 159668SW.BIN
Binary for FLASH ROM (IC1): 159670SW.BIN
Known Bugs and Limitations
It is not possible to flash upgrade a currently installed copy of the 4.114 firmware.
Currently under review.
Occasionally, the FPSC firmware reverts back to the version stored in the EPROM devices.
Currently under review.
Alerts for DriveBayLockSensor and PanelLockSensor are reset. Currently under review.
File List
Disk #1 /1
Volume in drive A is 159667SW
Volume Serial Number is E412-E3F0
Directory of A:\
13/02/97 10:01 131,072 159668SW.BIN
13/02/97 09:57 131,072 159669SW.BIN
13/02/97 09:57 131,072 159670SW.BIN
3 File(s) 393,216 bytes
1,064,448 bytes free |
3A
Beta
PN 159667SW |
17/03/97 |
Introduction
This is the fourth release of this product for the Discovery Server System.
Binary for EVEN address EPROM (IC3): 159669SW.BIN
Binary for ODD address EPROM (IC2): 159668SW.BIN
Binary for FLASH ROM (IC1): 159670SW.BIN
Changes Since Last Release
The PowerDescriptor reflects the state of the N+1 modules under the following Redundancy
conditions:
If system is Redundant i.e. PSURedundancy greater than 1, system is healthy.
If system is non redundant i.e. PSURedundancy equal to 1, degraded warning.
If system has less modules than real power available i.e. PSURedundancy equal to 0, system
critical error.
The variables shown below are now count type variables with the following bit field
assignments:
PSUInsertModule [0x0309]
| Bit |
Description |
| 1 |
PSU 0 inserted. |
| 2 |
PSU 1 inserted. |
| 3 |
PSU 2 inserted. |
| 4 |
PSU 3 inserted. |
| 5 |
BBU inserted. |
| 6 |
RESERVED. |
| 7 |
RESERVED. |
| 8 |
RESERVED. |
PSUHealthModule [0x030a]
| Bit |
Description |
| 1 |
PSU 0 ok. |
| 2 |
PSU 1 ok. |
| 3 |
PSU 2 ok. |
| 4 |
PSU 3 ok. |
| 5 |
RESERVED. |
| 6 |
DC Output Fan 1 Status. |
| 7 |
DC Output Fan 2 Status. |
| 8 |
RESERVED. |
The following new count type variables have also been
added:
PSURedundancy [0x030b]: Number of redundant N+1 modules.
PSUDC03Current [0x030c]: DC0-3 output of PSU (mA).
PSUDC4Current [0x030d]: DC4 output of PSU (mA).
PRF's, IPR's Fixed since last release
IPR03142 - Server DVT Unable to flash upgrade a currently installed copy of the 4.114
firmware.
IPR03260 - Server DVT FPSC firmware 4.12A occasionally reverts back to 4.114.
Known Bugs and Limitations
None.
File List
Disk #1 /1
Volume in drive A is 159667SW
Volume Serial Number is D413-15FE
Directory of A:\
10/03/97 15:33 131,072 159668SW.BIN
10/03/97 15:33 131,072 159669SW.BIN
10/03/97 15:33 131,072 159670SW.BIN
3 File(s) 393,216 bytes
1,064,448 bytes free |
3B
Beta
PN 159667SW |
27/05/97 |
FT4200 FPSC F/W Binary
for EVEN address EPROM (IC3): 159669SW.BIN
Binary for ODD address EPROM (IC2): 159668SW.BIN
Binary for FLASH ROM (IC1): 159670SW.BIN
Changes Since Last Release
- The state of the CircuitBreakerSense variable was incorrectly reported -
the cause of this problem has been traced to a hardware bug in the PSU, this version of
firmware incorporates a temporary fix to remove the fault symptom.
- Removed sampling of PSU variables to obtain the best possible value for a
variable - this operation was found to be too costly in terms of processor time.
Known Bugs and Limitations
Required FPSC to be reset before any variables would show.
File List
Disk #1 /1
Volume in drive A is 159667SW
Volume Serial Number is DC90-302B
Directory of A:\
27/05/97 11:31 131,072 159668SW.BIN
27/05/97 11:31 131,072 159669SW.BIN
27/05/97 11:31 131,072 159670SW.BIN
3 File(s) 393,216 bytes
1,064,448 bytes free |
3C
Beta
PN 159667SW |
09/07/97 |
FT4200 FPSC F/W Binary
for EVEN address EPROM (IC3): 159669SW.BIN
Binary for ODD address EPROM (IC2): 159668SW.BIN
Binary for FLASH ROM (IC1): 159670SW.BIN
Changes Since Last Release
It has been found that the I2C CONFIGURATION and SITUATION registers in
the PSU are susceptible to noise - therefore value sampling has been extended to cover
these two registers.
The behaviour of the TimeOnCharge variable observes the following
conditions:
- The TimeOnCharge variable is no longer cleared when the system enters the
BrownOut PowerModeand returns to PowerGood before the BrownOut timeout period has elapsed.
- Should the PowerMode degrade before BrownOut the behaviour of the
TimeOnCharge variable is unaltered.
Fixed since last release
Required FPSC to be reset before any variables would show.
Known Bugs and Limitations
None.
File List
Disk #1 /1
Volume in drive A is 159667SW
Volume Serial Number is ECCB-09A7
Directory of A:\
08/07/97 13:54 131,072 159668SW.BIN
08/07/97 13:54 131,072 159669SW.BIN
08/07/97 13:54 131,072 159670SW.BIN
3 File(s) 393,216 bytes
1,064,448 bytes free |
3D
Beta
PN 159667SW |
29/07/97 |
FT4200 FPSC F/W Binary
for EVEN address EPROM (IC3): 159669SW.BIN
Binary for ODD address EPROM (IC2): 159668SW.BIN
Binary for FLASH ROM (IC1): 159670SW.BIN
Changes Since Last Release
The behaviour of the TimeOnCharge and BatteryLife variables observe the
following convention:
- During BROWNOUT the value of the database variables are not reduced by
10% of their original value.
- Should the PowerMode degrade beyond BROWNOUT the behaviour of the
TimeOnCharge and BatteryLife variables are unchanged.
The above change cures the BatteryLife problem reported.
Fixed since last release
None.
Known Bugs and Limitations
None.
File List
Disk #1 /1
Volume in drive A is 159667SW
Volume Serial Number is E0C4-070A
Directory of A:\
29/07/97 11:48 131,072 159668SW.BIN
29/07/97 11:48 131,072 159669SW.BIN
29/07/97 11:48 131,072 159670SW.BIN
3 File(s) 393,216 bytes
1,064,448 bytes free |
3
Release
PN 159667SW |
26/09/97 |
FT4200 FPSC F/W Binary
for EVEN address EPROM (IC3): 159669SW.BIN
Binary for ODD address EPROM (IC2): 159668SW.BIN
Binary for FLASH ROM (IC1): 159670SW.BIN
Changes Since Last Release
- Redefined PSUHealthModule and PSUInsertModule to be of type count.
- Added count type variables PSURedundancy, PSUDC03Current, and
PSUDC4Current.
- Sampling has been extended to cover the PSU CONFIGURATION and SITUATION
registers.
- When the system goes into BROWNOUT the database values of BatteryLife and
TimeOnCharge are not updated.
- Added timeout value to I2C control register polling.
Fixed since last release
- Unable to flash upgrade a currently installed copy of the 4.114 firmware.
- FPSC firmware 4.12A occasionally reverts back to 4.114.
- Incorrect reporting of CircuitBreakerSense variable.
- Required FPSC to be reset before any variables would show.
File List
Disk #1 /1
Volume in drive A is 159667SW
Volume Serial Number is C4C4-4711
Directory of A:\
26/09/97 12:39 131,072 159668SW.BIN
26/09/97 12:39 131,072 159669SW.BIN
26/09/97 12:39 131,072 159670SW.BIN
3 File(s) 393,216 bytes
1,064,448 bytes free |
