|
|
|
|
|
                   |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Release | Date | Changes | |||||||||||||||||||||||
| BETA 1A PN 156071SW |
Introduction | This disk is a collection of utilities and the binary images required to update (or in some cases program for the first time) all the Flash-based firmware on Shogun. It is primarily intended for use by Apricot manufacturing, but will also be the means by which BIOS updates are released from R&D for distribution to the field. | |||||||||||||||||||||||
| Contents |
|
||||||||||||||||||||||||
| These items have all previously been issued to SVG under their own part numbers, and most will continue to be so (since they are originated by more than one person). However this complete disk will be re-released each time any of it’s components change, and should therefore be all that is required to update a machine to the latest versions of firmware. | |||||||||||||||||||||||||
| Operation | As mentioned above there are two potential users of the disk, production staff at the factory and engineers (or possibly end-users ?) in the field. The former should simply boot from it, and wait for the following menu to appear - | ||||||||||||||||||||||||
| Apricot Computers Limited, Copyright
1995 Shogun Firmware Upgrade Diskette REL1A 19/09/1995 1) SMIC BIOS. 2) Motherboard BIOS (With Conversion BG0-}BG0S). 3) User Binary. 4) Motherboard BIOS (Without Conversion BG0S-}BG0S). 5) File Information. 6) Reboot Machine. 7) Display Current Firmware Versions. 8) Display Out Of Date Firmware Versions. Please Select Required Option Or 0 to Exit ... ? |
|||||||||||||||||||||||||
| Selecting options 1, 2, & 3 will
upgrade each BIOS part in turn. When option 3 has completed the machine will perform a
reboot, after which all firmware should be up-to-date. Option 8 can be used to confirm
this. If the disk is being used to update a single component (e.g. a last-minute release /
re-work scenario) then just the appropriate menu option should be selected, followed by
the reboot choice. Firmware upgrades in the field can be performed either locally or remotely. In both of these cases the programming utilities (JFLASH, FMUP.EXE, etc.) are run from the Flash Disk, with the floppy just being used to supply the binary image files. In the case of remote upgrades it will be inserted into the drive on the SMA machine, locally in the actual Shogun’s drive. Note for local updates of the m/b BIOS it is slightly quicker simply to boot from the floppy, and use the factory menu (option 4), since copying files from floppy to the Flash Disk is currently rather slow. |
|||||||||||||||||||||||||
| Notes | There is insufficient space on the disk
to include the utility for updating the FPSC firmware. This option is however available on
the Flash Disk. The version-checking utility, GETVERS.EXE, should be added to the factory end-of-line Diagnostics disk, to ensure that all machines are shipped with the correct flash firmware revisions. The current Flash Disk install floppy does not label the image it creates, so the release number cannot be reported to the FPSC, or checked by GETVERS. This will hopefully be fixed in the next release, and therefore VERSIONS.INI will need updating. |
||||||||||||||||||||||||
| RELEASE 1 PN 156071SW |
Contents |
This release is functionally unchanged from the previous BETA version. | |||||||||||||||||||||||
|
|||||||||||||||||||||||||
| BETA 2A PN 156071SW. |
This release includes the Apricot customised version of the Intel 1.04 XX motherboard BIOS, PN 155309SW, version BETA 1E. | ||||||||||||||||||||||||
| BETA 2B PN 156071SW. |
Introduction | This release updates the XX motherboard
BIOS to version 0.02.02.BG0S ("Beta 2.02"), the change from Beta 2.01 being a
possible fix for the SMI test failures / CMOS corruption recently observed in Glenrothes
and Japan. See attached Intel release note for details. I have also replaced the 3.006 FPSC binary with version 3.008, and updated the Flash Disk label in VERSIONS.INI to "REL2B". |
|||||||||||||||||||||||
| Contents |
|
||||||||||||||||||||||||
| RELEASE 2 PN 156071SW. |
Contents | This is the production release of the Rel 2B disk which has been on Beta since 24th Nov last year. See previous release notes for details of the incremental changes since Rel 1. The only change in this version is removal of the Beta banner from the Motherboard BIOS, and updates of the strings in VERSIONS.INI (Flash Disk is now "REL2_00"). | |||||||||||||||||||||||
|
|||||||||||||||||||||||||
| Release | Date | Changes |
| 0.02.03 BETA PN 155309SW |
Issues resolved in this release, D2445, EISA cards are now detected in slot 6. D1996, ‘Hobbes’ keylock control is now implemented in the system BIOS. D1949, 32-bit EISA NVRAM access via INT 015h is now supported. D2367, Add-in 787x cards are no longer disabled when on-board SCSI BIOS scan is disabled. D2041, PCI POST test errors are no longer disabled. D2321, ‘Flash’ recovery with custom system BIOS is now supported. D2434, IRQ12 is now not mis-assigned if a mouse is not attached. D2423, Error log now matches INT 015h, function 021h. ‘Three-mode’ FDU support now works on drive B: |
|
| Features added or changed in this
release, This BIOS now includes SCSI CD-ROM boot code. ‘Cancel Write Back’ is now set automatically. Users also have the option of disabling ‘Cancel Write Back’, however, they cannot manually enable the feature. The user is no longer requested to ‘press a key to continue’ when an error occurs and no keyboard is attached to the system. Custom BIOS support is implemented in this release due to updated ‘Flash’ tables. The LCD display during POST has been altered. It now shows the BIOS version string on the second line of the display, and the ‘countdown code’ in the top-left corner, to prevent display wrapping |
||
| Outstanding issues, D2408, Turbo/DeTurbo fails on FAB 5. D2413, Turbo/DeTurbo fails on FAB 5A. D2425, ‘HIMEM.SYS’ will not load if system memory is re-sized from >64Mb to <64Mb. D2205, FDU boot in ‘secure’ mode requires the user to enter the password twice. IRQ11 does not ‘respond’ correctly for ‘Hobbes’. 133Mhz CPUs are not automatically detected. |
||
| Release 1d PN 155309SW. |
Introduction | This is the fourth release within
R&D of the BIOS for XX Shogun motherboards, and consists of the following - MS-DOS 6.22 1.44MB boot floppy Extracted contents of Intel FMUPDISK.ZIP file (31/8/95), which contains the flash programming utility and BIOS version 0.03.01.BG0S binaries Removed unnecessary files (BG0SBG0S.BAT, BIOSUP.EXE, CHANGES.TXT, CUTUSER.BAT, FLASH32.PCX, LOCAL.CFG, README.TXT and SHOWHDR.EXE) |
| Testing | On a system with Fab-5 motherboard, BIOS
Version 0.01.01.BG0S, and no SMIC - Booted from the floppy (AUTOEXEC.BAT runs FMUP.EXE) Selected Update Flash Memory Area from a File, then Update System BIOS+User Area Tabbed to the file list, selected 1B03BG0S.BIO, and answered yes to the "do you wish to continue" question Programming completed successfully, selected continue to reboot, and observed that the new BIOS signed on correctly ("0.03.01.BG0S - Beta 1.03") |
|
| Notes | This disk will only work on machines
which already contain the custom ‘Apricot’ XX BIOS (recognisable by the last
section of it’s version number being "BG0S"), i.e. cannot be used to
program virgin boards from Intel. These must be upgraded in a two-stage process, firstly from Intel’s 1.03.00.BG0_ to the Apricot 0.01.01.BG0S, using the previous release of this disk, and then from 0.01.01.BG0S to 0.03.01.BG0S. I appreciate that this is likely to cause problems for Glenrothes, having to work with 2 revisions of a item with the same part number, so will probably release a new disk for them which allows direct conversion from BG0_ to BG0S No Intel release notes are available for this version of the BIOS, but essentially it should be identical to 0.01.01.BG0S with the exception of default values for some configuration options. To cut a long story short there was a degree of misunderstanding over exactly what customisations Apricot needed, leading to a number of system-management voltage / temperature monitoring channels being enabled when they shouldn’t be. The attached email defines what the new defaults are (note, they have been implemented in the BIOS, not the SCU as previously), and needs to be checked by SVG. The Flash upgrade process still causes any user-binary present to be erased, so for correct operation of the SMIC card FMUP.EXE must be used to reload it. |
|
| Rel 1E 155309SW |
Introduction | Although this disk (155309SW) was
effectively superseded by the menu-driven Shogun Firmware Update Disk (156071SW), a new
release from Intel of the standard XX BIOS requires that it be updated once more. This is because the necessary files to allow conversion back from the BG0S custom BIOS have not been supplied, meaning that the only way to update our machines to this version is via the Flash recovery procedure described below. When the custom build of this BIOS does become available (probably in a few weeks time) a new version of 156071SW will be released, and it is only that disk which will go final for release to the factory. |
| Testing | On a system with Fab-5 motherboard, BIOS
Version 1.00.01.BG0S, User-Binary Version 1.00, Rev/B SMIC, and SMIC BIOS Version 1.00 -
Moved the m/b ‘Boot Block’ jumper (located just below the top CPU-card slot)
from ‘Disable’ to ‘Enable’ Powered on with this floppy in the drive Listened for single high-pitched beep, followed by the drive stepping and about a minute later another 2 beeps (confirming that programming has completed successfully) Powered off, set the Boot Block jumper back to ‘Disable’, powered on again, and confirmed that the new BIOS signs on - 1.00.04.BG0. |
|
| Notes | The above steps cause the User Binary to
become erased (the SMIC BIOS will issue an error message to this effect) - use menu option
3 on the Shogun Firmware Update Disk to replace it. Since 1.00.04 is a fairly major update from Intel it would probably be wise to reset the CMOS (using the procedure described in the recent SCU release note, 155160SW Rel 2A) after re-programming. |
| Release | Section | Changes | ||||||||||||
| BETA 1.00.07 PN 155683SW. |
File details |
|
||||||||||||
| Programming |
|
|||||||||||||
| Description | The user-binary is a small piece of
code, written by Apricot, which provides a s/w interface between the Intel XX and Shogun
SMIC BIOS’s. It is stored in an independently programmable 8k page of the Intel Flash, and is called at a number of stages (scan points) throughout POST, where it simply passes control on to routines in the SMIC BIOS. Design of the user-binary has been kept as simple as possible, with all logic (apart from initial SMIC detection and a ROM paging / checksum test) being contained in the SMIC BIOS. This way field upgrades of the user-binary (which, using Intel Flash programming utilities, is less under our control than JFLASH) should rarely, if ever, be required. The user-binary is also called towards the end of Intel’s SMI handler, allowing the SMIC BIOS to report fatal errors (double-bit ECC, PCI PERR / SERR, bus timeouts, etc) to the FPSC. |
|||||||||||||
| Known omissions | SMIC BIOS debug-message enable / disable
flag controlled by switch in addition to CMOS location Removal of Intel and Shogun references from WHAT string More meaningful description in the file header (currently displayed, when running FMUP, as "This is a comment") |
|||||||||||||
| Known problems | Some SMIC ROM errors, from self-tests performed by the user-binary, may not be reported [too much error reporting moved out of the user-binary into the option-ROM] | |||||||||||||
| Additional information | This version of the user-binary must be used in conjunction with SMIC BIOS 1.00.07 or later (by happy coincidence both version numbers are currently the same). It is hoped that revisions of the SMIC BIOS between now and production will not require further changes to the user-binary, or visa-versa. | |||||||||||||
| What string | Intel XX Shogun User Binary Version 1.00.07, 27th July 1995 Copyright (C) 1995 Apricot Computers Ltd |
|||||||||||||
| BETA 1.00.09 PN 155683SW checksum 0D77. |
File details |
|
||||||||||||
| Programming |
|
|||||||||||||
| Changes from version 1.00.07 | Problem of a maximum of 8 entries in
each scan point being called fixed. This means that some SMIC BIOS code that might not have been called in the past will now be called. This included Security and Console Redirection. Code now checks for the presence of the standard option ROM signature in page 0 after detecting the presence of a valid page 1 signature. SMIC BIOS debug-message enable/disable flag now controlled by a switch in addition to CMOS location. Debug is turned on by switch #1 of the SMIC switches being set to the off position. Removal of Intel and Shogun references from WHAT string. Now just displays "SMIC User Binary". Added more meaningful description to the .USR file header. The version number and the date are now displayed when FMUP.EXE is run and user binary update is selected. |
|||||||||||||
| Known omissions | None | |||||||||||||
| New known problems | None | |||||||||||||
| Additional information | This version of the user-binary must be used in conjunction with SMIC BIOS 1.00.07 or later | |||||||||||||
| Testing | Problem of a maximum of 8 entries in
each scan point being called - tested by loading the new userbin.usr into a machine and
turning on debug via the cmos and checking that security is called. Code now checks for the presence of the standard option ROM signature in page 0 after detecting the presence of a valid page 1 signature - tested by checking no error reported by new code. SMIC BIOS debug-message enable/disable flag controlled by a switch - tested by disabling debug via cmos and setting switch #1 on and making sure security does not display debug then switching #1 off and checking security displays debug messages. Removal of Intel and Shogun references from WHAT string, now displays SMIC User Binary - tested by running the what.exe program on userbin.usr. See results below. More meaningful description in the file header - tested by running the FMUP.EXE program and loading the new userbin.usr and checking the message and date string were correct. |
|||||||||||||
| What string | SMIC User Binary Version 1.00.09, 10th August 1995 Copyright (C) 1995 Apricot Computers Ltd |
| Release | Section | Changes | |||||||||||||||||||||||||||||||||||||||||||||||||||||
| version 1.00.02 BETA PN 123554SW checksum 4100. |
Please note that this BIOS will only work on rev. A cards and NOT rev. B. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||
| version 1.00.05 BETA PN 123554SW checksum F600 |
Included in this release, | Inventory reporting (CPU, L2 cache,
memory, EISA & PCI cards, serial, . parallel and FDU). Time synchronisation (FPSC clo Inventory reporting (CPU, L2 cache, memory, EISA & PCI cards, serial, . parallel and FDU). Time synchronisation (FPSC clock set from m/b RTC). Sub-system control (CPU enable/disable). Ethernet card node address reporting (3COM 3C509, 3C579 and 3C595). Boot control ("Press F2 to boot from Flash disk"). Flash disk (2Mb drive C: emulation). AIS Manager (SMIC detection API for Flash disk install S/W). FPSC and pass-through serial port configuration (from SMIC switches) 32Kb option ROM header (to prevent m/b Adaptec BIOS locating over SMIC SRAM). CMOS check/set (to ensure that ‘user binary’ calling is always enabled, and D000-D800 shadowing is disabled. Missing ‘user binary’ detection and reporting. ck set from m/b RTC). Sub-system control (CPU enable/disable). Ethernet card node address reporting (3COM 3C509, 3C579 and 3C595). Boot control ("Press F2 to boot from Flash disk"). Flash disk (2Mb drive C: emulation). AIS Manager (SMIC detection API for Flash disk install S/W). FPSC and pass-through serial port configuration (from SMIC switches) 32Kb option ROM header (to prevent m/b Adaptec BIOS locating over SMIC SRAM). CMOS check/set (to ensure that ‘user binary’ calling is always enabled, and D000-D800 shadowing is disabled. Missing ‘user binary’ detection and reporting. |
|||||||||||||||||||||||||||||||||||||||||||||||||||||
| Known omissions, | Further inventory reporting (SMIC, m/b
and ‘user binary’ BIOS version numbers). Further boot control (from FPSC variable choice). Further Ethernet card node address reporting (support for more cards). Security (boot disable when FPSC security variable is set and chassis doo Further inventory reporting (SMIC, m/b and ‘user binary’ BIOS version numbers). Further boot control (from FPSC variable choice). Further Ethernet card node address reporting (support for more cards). Security (boot disable when FPSC security variable is set and chassis door is locked / unlocked). Console redirection (remote display of POST messages and running of BIOS setup / SCU). Further self tests (SMIC SRAM, serial ports and Flash disk device). AIS Manager ‘boot reason’ function. Serial port configuration from SCU menu option (cf switches). Fatal error handler. CPU speed independent timing for message delays. Product name (FT//mp ?) display. Further CMOS check/setting (C800-D000 shadowing control for alternate SMIC address). POST progress monitoring (FPSC ‘3000’ series LCD codes). Non-fatal POST error reporting (to FPSC). r is locked / unlocked). Console redirection (remote display of POST messages and running of BIOS setup / SCU). Further self tests (SMIC SRAM, serial ports and Flash disk device). AIS Manager ‘boot reason’ function. Serial port configuration from SCU menu option (cf switches). Fatal error handler. CPU speed independent timing for message delays. Product name (FT//mp ?) display. Further CMOS check/setting (C800-D000 shadowing control for alternate SMIC address). POST progress monitoring (FPSC ‘3000’ series LCD codes). Non-fatal POST error reporting (to FPSC). |
||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Known problems, | DOS FPSC utilities, such as TEST434
(Front panel test) or FPSCVAR.EXE (debug variable reading program), do not work with
certain SMIC serial port IRQ settings. The machine will hang if Flash disk boot is selected before the SMIC 28F016 device has been initialised. ‘CPU x failure’ messages will be displayed by POST when CPUs are disabled via the SMA. There is a long delay between VGA BIOS signon and SMIC serial port messages when no FPSC is present. |
||||||||||||||||||||||||||||||||||||||||||||||||||||||
| NOTES | This BIOS must be used in conjunction
with ‘user binary’ version 1.00.02 or later. Debug message output from some modules can be enabled by setting CMOS location 033h, bit 6. |
||||||||||||||||||||||||||||||||||||||||||||||||||||||
| version 1.00.06 BETA PN 123554SW checksum 2600. |
Changes from version 1.00.05 | Added sub-system control (CPU enable /
disable) Added missing user-binary reporting Added motherboard BIOS version number reporting (to FPSC) Added Flash Disk boot control from FPSC variable choice, and moved earlier in POST (before Adaptec SCSI BIOS signon) Added security (boot disable when FPSC ‘security’ variable is set, chassis door is l Added sub-system control (CPU enable / disable) Added missing user-binary reporting Added motherboard BIOS version number reporting (to FPSC) Added Flash Disk boot control from FPSC variable choice, and moved earlier in POST (before Adaptec SCSI BIOS signon) Added security (boot disable when FPSC ‘security’ variable is set, chassis door is locked, and the reboot / power-on was instigated locally) Added self-tests for SMIC SRAM, serial port I/O for Console Redirection, and Flash Disk device Added AIS manager ‘boot reason’ function Added fatal error handler (memory only - awaiting further details from Intel for adapters) Added POST progress monitoring (FPSC ‘3000’ series LCD codes) Added non-fatal POST error reporting (to FPSC) SMIC serial port configuration now controlled from SCU menu options (cf switches) Fixed SMIC code and SRAM page selects after a flash disk boot. This was leaving code page 7, SRAM page 3 and 16k page size selected. Now reset to code & SRAM page 0 and 32k page size. Fixed a number of inventory reporting bugs (symptom = incorrect SMA sub-system display) ocked, and the reboot / power-on was instigated locally) Added self-tests for SMIC SRAM, serial port I/O for Console Redirection, and Flash Disk device Added AIS manager ‘boot reason’ function Added fatal error handler (memory only - awaiting further details from Intel for adapters) Added POST progress monitoring (FPSC ‘3000’ series LCD codes) Added non-fatal POST error reporting (to FPSC) SMIC serial port configuration now controlled from SCU menu options (cf switches) Fixed SMIC code and SRAM page selects after a flash disk boot. This was leaving code page 7, SRAM page 3 and 16k page size selected. Now reset to code & SRAM page 0 and 32k page size. Fixed a number of inventory reporting bugs (symptom = incorrect SMA sub-system display) |
|||||||||||||||||||||||||||||||||||||||||||||||||||||
| Known omissions | Console redirection (remote display of
POST messages and running of BIOS Setup / SCU) Further inventory reporting (SMIC and user-binary BIOS version numbers) Possibly further ethernet card note address reporting (supporting more cards) CPU-speed independent timing for message delays Self test for FPSC serial port I/O Product name (FT//mp ?) display |
||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Additional information | This BIOS must be used in conjunction
with user-binary version 1.00.04 or later. The system will hang when attempting to boot
from flash disk with earlier versions of the user-binary. Debug message output from some modules can be enabled by setting CMOS location 33h, bit 6 |
||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Testing | Time synchronisation has been tested but
ethernet card node address reporting has not been fully verified. Inventory reporting has
been tested further with the SMA but should still be thoroughly checked against a
‘golden’ FPSC variable dump. Sub-system control is not yet supported by the SMA,
so has not been tested. AIS manager has now been tested (by calling it from debug). The
self-tests have not been run against faulty hardware. All recent development has been on Rev/B SMIC’s, in Fab-5 XX motherboards, mostly with a single CPU and memory card, Intel BIOS version 0.02.03.BG0 (‘Beta-15’), and SCU version 3.09 / overlay 34. |
||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Switch setting information No longer relevant - SMIC serial ports now configured by the SCU. |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||
| LCD codes |
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||
| What strings | Shogun SMIC BIOS Page 0 Version 1.00.06,
16th June 1995 Shogun SMIC BIOS Page 1 Version 1.00.03, 23rd June 1995 Shogun SMIC BIOS Page 2 Version 1.00.04, 22nd June 1995 Shogun SMIC BIOS Page 3 Version 1.00.01, 1st June 1995 Shogun SMIC BIOS Page 4 Version 1.00.02, 7th June 1995 SMICPG5.BIN version 1.00.05, 22nd June 1995 Shogun SMIC BIOS Page 6 Version 1.00.03, 22nd June 1995 Shogun SMIC BIOS Page 7 Version 1.0.04, 22nd June 1995 |
||||||||||||||||||||||||||||||||||||||||||||||||||||||
| version 1.00.07 BETA PN 123554SW checksum 1100. |
Changes from version 1.00.06 | Added the long-awaited console
redirection (aka pass-through mode: remote display of POST messages and running of BIOS Setup / SCU) conditional on an FPSC variable set / cleared by the SMA. Speed is automatically set from the ModemPortBaudRate variable. Added sub-system control (CPU enable / disable). Machine has to be rebooted for the changes to take effect, so a message that this is occurring is printed. Note that Intel use the same CMOS location for CPU disable and failure, so when you disable a CPU from the SMA it will actually be reported as having failed (red cross next to picture on SMA ‘tree’ display, plus error message printed / logged by POST). There’s nothing really we can do about this, apart from to document it. Extended fatal-error reporting to include PCI (PERR and SERR) and ISA / EISA (I/O channel check and bus timeout). Note, we are working with incomplete specifications from Intel here, so this needs extensive testing. Moved serial port address / IRQ setup and reporting to before FPSC comms initialisation (actually to before serial self-tests, which are in turn before this), and therefore had to remove the 3500 / 3D00 LCD outputs Added SMIC BIOS version number reporting (to FPSC) Added self-tests and for both SMIC serial ports (basic I/O, loopback, interrupt, and FIFO) Added clear-screen and SMIC BIOS signon at first available user-binary scan point (between Cirrus and Intel BIOS signons), and added logic to suppress the option-ROM signon if the earlier one has occurred Added SMIC ROM paging and checksum self-test error reporting (formerly done by the user-binary) Suppressed individual ROM page WHAT strings - the overall SMIC BIOS version number and date is now set by ‘branding’ the combined image just before release (allowing consecutive version numbers to be guaranteed) Moved all SMIC self-test error reporting into a separate routine towards the end of POST (may be some time after the corresponding test, but necessary for the messages not to be erased by the clear-screen before Intel’s BIOS signon), and added "Press F1 to continue" prompt / wait when an error occurs Added test and error message for SMIC serial port IRQ’s being set to none (currently a valid option in the hardware and CFG file) Removed simulated user-binary scan point 40h (work-round for Intel BIOS bug, fixed in 1.00.03.BG0 and later) Moved Flash Disk boot prompt and action back to later in POST (undoing the change made between SMIC BIOS versions 1.00.05 and 1.00.06). Although this means you have to now have to sit through the Adaptec signons again it appears to be necessary for the SCU to run reliably. Moved EISA card inventory reporting to earlier in POST (int 15 function D801 call was failing for some unknown reason at the later position, causing incorrect adapter configuration information to be sent to the FPSC) Added a routine which sends "2000" to the front-panel LCD (NextBootStage FPSC variable) at the end of POST. The intention of this is to stop the PostExectionTimer watchdog from expiring when the OS loads, but there is currently some confusion about which value should be used, so the number may need to be changed in the next SMIC BIOS or FPSC firmware release. Extended inventory reporting validity checking to include Intel ‘CMOS’ failures in addition to ‘NVRAM’ Added support for bus numbers changing when a card with a PCI bridge device (e.g. the Adaptec 3940) is present, to the PCI-card inventory reporting and ethernet node address reporting code Fixed bug which caused machines to hang early in POST, with 3200 on the front-panel LCD, if the Intel error log was corrupted in a particular way (record length of zero) Added error message for front-panel communication failures (printed immediately, and logged, if occurs during initial ‘presence’ test, logged for printing / Press F1 later if occurs at any other time) Reduced the number of retries in the FPSC test, from 20 to 4, eliminating the impression of a system hang (was actually something like a 2 minute timeout, now approx 20 seconds) when the SMIC-to-FPSC ribbon cable is disconnected Extended an internal delay count in the low-level FPSC comms to eliminate the danger of timeouts on machines with faster CPUs Reversed the byte ordering of the FPSC ethernet node address variables (as requested by s/w dev for compatibility with their released demons and MACADDR utility) Added test / non-fatal error message for SMIC CFG file not having been loaded (when the SCU was run) Fixed problem with false SRAM failure reporting when SMIC base address set to C800h (cf D000h) Removed "Testing SMIC SRAM" message (test still included though, just doesn’t print anything) Fixed incorrect Flash Disk self-test LCD codes (was 3620 / 3D20, is now 3720 / 3F20) |
|||||||||||||||||||||||||||||||||||||||||||||||||||||
| Known omissions | Remote running of BIOS Setup (awaiting
details of F1-pressed flag location from Intel) Skipping of SMIC "Press F1 to continue" prompt when automatic failure recovery is enabled FPSC POST execution timer cancellation when booting from Flash Disk Bus number translation (due to bridge card presence) in the PCI fatal error reporting module Debug message flag controlled by SMIC switch in addition to CMOS location (this will actually be a user-binary change) Debug message output from FPSC comms and inventory reporting modules Logging of Flash Disk device self-test errors Making the serial port information printing a debug-only message ? SMI handler self-test (deliberate generation of a single-bit memory error) Possible checking / setting of CMOS location to automatically enable Intel’s SMI handler (error logging) Possible improvements to the way the inventory reporting and fatal error code looks for the Intel error log (we currently bypass one of their pointer tables) Clearing of Intel error log when it becomes [nearly ?] full Error message text review / tidy-up (e.g. for consistency of names with SMA and documentation) Possibly further ethernet card note address reporting (supporting more cards) CPU-speed independent timing for message delays and test timeouts User-binary BIOS version number reporting (to FPSC) Logic to prevent the console redirection code being called when no IRQ has been assigned to the pass-through serial port Check that all code supports alternate SMIC address (i.e. no hard-coded D000h segment assumptions) Product name (FT//mp and/or Shogun ?) display |
||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Additional information | This BIOS must be used in conjunction with user-binary version 1.00.07 or later, and Intel XX BIOS version 0.01.01BG0S (Beta 1.01) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||
| New known problems Possible OS unreliability due to SMIC BIOS extending the duration of Intel’s periodic SMI (see email to Risk User, 21/7/95) Unexpected "CMOS changed by SMIC BIOS" message (at totally the wrong place in POST) observed on one development machine. This may be a page-switching [timing / hardware ?] problem. Some SMIC ROM errors, from self-tests performed by the user-binary, may not be reported [too much error reporting moved out of the user-binary into the option-ROM] Addition of CPU enable / disable code probably means that genuine CPU failures are not reported (or are only reported once). Extra SMIC BIOS & SMA work is being considered to fix this. BIOS version reporting does not work with FPSC firmware version 3.003 (incorrect variable attributes). Tak is aware of this and is has been / will be fixed in his next release. Floppy errors (apparently causing disc corruption, even when just reading), possibly related to console redirection being enabled. This may not be an issue if the Flash Disk AUTOEXEC.BAT always loads it’s own int-60 handler. Machine hangs if you run JFLASH (to update the SMIC BIOS) when the Intel BIOS error logging option is enabled. This is understandable, since the SMIC BIOS includes code which is in the SMI chain, and would presumably also happen when you update the user binary (unless FMUP / BIOSUP are clever enough to disable the periodic SMI during this time ?). This will be fixed in a future release of JFLASH. Serial port FIFO tests do not fail on a board fitted with PC16550DV UARTS, which are claimed not to have a FIFO ! Production boards will not be using this part, but people should be aware that not all beta-build SMICs have been reworked to the correct device (TL16C550AFN) The PERR switch on Dave Wright’s PCI error-generation card has no effect (latest indications from Intel are that this signal is not connected to their error monitoring hardware - ESC / INCA), and the SERR switch causes the machine to hang without apparently calling the SMIC BIOS SMI handler (although this may be due to Intel’s event logging being disabled - menu option has been removed from latest SCU and there is uncertainty about what it gets defaulted to). |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Testing | Most changes and additions have been
tested (although nowhere near exhaustively, due to the pressures of time) during
development, but none apart from version number signon and Flash Disk boot have been
re-verified with the final released binary. We continue to use Rev/B SMIC’s, in Fab-5 XX motherboards, mostly with a single CPU and memory card, but now with Intel BIOS version 0.01.01BG0S (Beta 1.01), and Apricot SCU disk Rel 1D Beta (Intel SCU Version 3.09, Overlay Beta 00.35). SMA and FPSC versions vary. Lest it be forgotten, I repeat again what was said in the last two SMIC BIOS release notes, that inventory reporting needs to be thoroughly checked against a ‘golden’ FPSC variable dump. There is a significant risk of this containing errors due to incomplete specification of all the enumerated values, and of things going wrong when the Intel BIOS or silicon changes (e.g. Fab-5 to 5-A). |
||||||||||||||||||||||||||||||||||||||||||||||||||||||
| LCD codes |
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||
| WHAT strings | Public WHAT string SMIC BIOS Version 1.00.07 27th July 1995 Copyright (C) 1995 Apricot Computers Ltd |
||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Internal WHAT strings SMICPG0.BIN version 1.00.10, 27th July 1995 SMICPG1.BIN version 1.00.05, 27th July 1995 SMICPG2.BIN version 1.00.07, 27th July 1995 SMICPG3.BIN version 1.00.02, 25th July 1995 SMICPG4.BIN version 1.00.03, 25th July 1995 SMICPG5.BIN version 1.00.08, 26th July 1995 SMICPG6.BIN version 1.00.07, 27th July 1995 SMICPG7.BIN version 1.00.06, 25th July 1995 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||
| version 1.00.08 BETA PN 123554SW checksum 6D00. |
File details |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||
| Programming |
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Notes | The purpose of this release is to allow
SVG testing of pass-though mode / console redirection to begin. Accordingly it does not
include any IPR fixes or recently developed code in other areas of the SMIC BIOS (e.g. all
WHAT strings except page 3 are identical to the last release). The ‘know omissions’ section below has been organised under 3 headings, the meaning of which are explained in the footnotes. Shaded rows represent completed items of work. |
||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Changes from version 1.00.07 | Added logic to disable console
redirection whilst the DOS file-transfer utility is running Added support for screen update request function to console redirection code (to allow the SMA to get redraws when first connected, or if image becomes corrupted) Fixed "floppy errors (causing disc corruption, even when just reading), when console redirection is enabled" problem Added a new int-60 function to return the original BIOS timer-tick vector (allowing the Flash Disk menu s/w to remove the SMIC BIOS / user-binary from the interrupt chain before reprogramming them) Added debug output (ASCII characters at top left of screen) to pass-through comms module, conditional on the user-binary debug flag [CMOS or SMIC switch] |
||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Known omissions | Functional SMI handler self-test (deliberate generation of a single-bit memory error) Remote running of BIOS Setup (awaiting SMA and FPSC support) Skipping of SMIC "Press F1 to continue" prompt when automatic failure recovery is enabled FPSC POST execution timer cancellation when booting from Flash Disk Check that all code supports alternate SMIC address (i.e. no hard-coded D000h segment assumptions) Debug message output from FPSC comms and inventory reporting modules Logging of Flash Disk device self-test errors Flash Disk version number reporting (to FPSC) Change end of POST NextBootStage marker from 2000 to 7FF0 (awaiting FPSC support) Clearing of Intel error log when it becomes nearly full User-binary BIOS version number reporting (to FPSC) Logic to prevent the console redirection code being called when no IRQ has been assigned to the pass-through serial port |
||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Cosmetic | Making the serial port information
printing a debug-only message Error message and serial port naming review / tidy-up (e.g. for consistency of names with SMA and documentation) Removal of clear-screen from option-ROM signon (partially explains unexpected "CMOS changed by SMIC BIOS" message mentioned in 1.00.07 release note) Product name (FT//mp and/or Shogun ?) display |
||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Dormant | Further ethernet card node address
reporting (supporting more cards) CPU-speed independent timing for message delays and test timeouts Improvements to the way the inventory reporting and fatal error code looks for the Intel error log (we currently bypass one of their pointer tables) Bus number translation (due to bridge card presence) in the PCI fatal error reporting module |
||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Additional information | This BIOS must be used in conjunction with user-binary version 1.00.09 or later, and Intel XX BIOS version 0.01.01BG0S (Beta 1.01) | ||||||||||||||||||||||||||||||||||||||||||||||||||||||
| New known problems | CMOS corruption from CPU enable /
disable reboot (IPR 1465, "Disabling 2nd CPU causes continuous reboot") Potential false serial-port test failures (-> no console redirection etc) when spurious data present n the UART receive buffer SMIC BIOS FPSC communications failures when no front-panel serial port IRQ selected Possible deficiencies in SMIC ROM checksum / page-validity test ? (system seen to hang on reboot after JFLASH failure) |
||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Testing | Console redirection was run on an SVG machine in the Chapel (the one furthest from the photocopier) with Intel BIOS version 0.01.01BG0S (Beta 1.01), Flash Disk Rel 1D, and SMA Rel 1F. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||
| WHAT strings | Public WHAT string SMIC BIOS Version 1.00.08, 22nd August 1995 Copyright (C) 1995 Apricot Computers Ltd |
||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Internal WHAT strings SMICPG0.BIN version 1.00.10, 27th July 1995 SMICPG1.BIN version 1.00.05, 27th July 1995 SMICPG2.BIN version 1.00.07, 27th July 1995 SMICPG3.BIN version 1.00.04, 18th August 1995 SMICPG4.BIN version 1.00.03, 25th July 1995 SMICPG5.BIN version 1.00.08, 26th July 1995 SMICPG6.BIN version 1.00.07, 27th July 1995 SMICPG7.BIN version 1.00.06, 25th July 1995 |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||
| version 1.00.09 BETA PN 123554SW checksum E100. |
Changes from version 1.00.08 | Added skipping of SMIC "Press F1 to
continue" prompt when automatic failure recovery is enabled Added logic to prevent console redirection being run when no IRQ has been assigned to the pass-through serial port (also logs a non-fatal error message, "Pass through port has no IRQ allocated") Added SMI handler & error-logging self-test (deliberate generation of a single-bit memory error) Extended Flash Disk tests to include check for device not being formatted Removed clear screen from option-ROM signon Added erasing of Intel error log when it becomes nearly full Added Flash Disk version number reporting (to FPSC). Also corrected possible bug in SMIC BIOS version number reporting. Console redirection now disabled at the end of POST if not booting from Flash Disk (o/w causes problems with graphical OS’s) Changed inventory-reporting code (floppy, parallel, serial, & memory) to be more tolerant of incomplete error log Extended PCI SERR fatal error handler - now acts on the bus ID (previously just set FatalErrorType variable) Fixed "SMIC BIOS FPSC communications failures when no front-panel serial port IRQ selected" problem Added debug message output from FPSC comms and inventory reporting modules Fixed IPR 1465, "Disabling 2nd CPU causes continuous reboot" Fixed unreliability in serial and parallel inventory reporting code (particularly when ports set to auto-configuration in the SCU) by getting information from chipset registers instead of CMOS. Also changed FPSC variable type for serial from choice to a count for consistency with the SMA. Changed end of POST NextBootStage marker from 2000 to 7FF0 Fixed IPR 1484, "BIOS does not report that SMIC is connected in EISA slot" Added forced screen update at the end of POST in pass-through mode to fix corruption caused by OS’s resetting the COM3/4 UART Added support for remote running of BIOS Setup (controlled by the FPSC SetUpStartRequest variable) Made the serial port information printing a debug-only message Fixed potential problems in the SMIC UART self-tests (disable loopback on completion of poll test, and interrupts after interrupt test) Fixed potential false serial-port test failures (-> no console redirection etc) when spurious data present n the UART receive buffer Added FPSC POST execution timer cancellation when booting from Flash Disk Added user-binary BIOS version number reporting (to FPSC) Added logging of Flash Disk device self-test errors [check this] |
|||||||||||||||||||||||||||||||||||||||||||||||||||||
| Known omissions | Functional None |
||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Cosmetic Error message and serial port naming review / tidy-up (e.g. for consistency of names with SMA and documentation) Product name (FT//mp and/or Shogun ?) display |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Dormant Further ethernet card node address reporting (supporting more cards) CPU-speed independent timing for message delays and test timeouts Improvements to the way the inventory reporting and fatal error code looks for the Intel error log (we currently bypass one of their pointer tables) Bus number translation (due to bridge card presence) in the PCI fatal error reporting module Check that all code supports alternate SMIC address (i.e. no hard-coded D000h segment assumptions) |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Additional information | This BIOS must be used in conjunction with user-binary version 1.00.09 or later, and Intel XX BIOS version 0.01.01BG0S (Beta 1.01) or later. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||
| New known problems FPSC communications failures when SMIC has not been configured (via ECU / !ACL0100.CFG) SMA only displays one of the SMIC resources (I/O, IRQ, etc) reported in the EISA descriptor |
|||||||||||||||||||||||||||||||||||||||||||||||||||||||
| LCD codes |
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||
| WHAT strings | Public WHAT string SMIC BIOS Version 1.00.09, 4th September 1995 |
||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Internal WHAT strings SMICPG0.BIN version 1.00.11, 4th September 1995 SMICPG1.BIN version 1.00.06, 4th September 1995 SMICPG2.BIN version 1.00.08, 4th September 1995 SMICPG3.BIN version 1.00.05, 4th September 1995 SMICPG4.BIN version 1.00.03, 25th July 1995 SMICPG5.BIN version 1.00.09, 4th September 1995 SMICPG6.BIN version 1.00.08, 4th September 1995 SMICPG7.BIN version 1.00.07, 4th September 1995 |
| Release | Changes |
| BETA 1A PN 155222SW. |
This is the initial release of the
Shogun Front Panel Systems Controller (FPSC) firmware and contains the following binaries, A) Systems Controller Firmware, version 3.001 Customising EPROM, IC3 - 155083SW.BIN Even, checksum AB10 IC2 - 155084SW.BIN Odd, checksum 6FF0 Flash - to be used when programming function is carried out by SMA. (Same contents as above files), SMC3001.BIN, checksum 1B00 B) Diagnostics Processor Firmware, version 3.00 87C51, SMIB006A.BIN, checksum 8E00 NOTES Reset control has been deleted. ‘Port80’ capturing added. M/B ‘Warm reset’ monitor added. |
| BETA 1B PN 155222SW |
Systems Controller Firmware, version
3.003 Customising EPROM, IC3 - 155083SW.BIN Even, checksum 2599 IC2 - 155084SW.BIN Odd, checksum D467 Flash - to be used when programming function is carried out by SMA. (Same contents as above files), SMC3003BIN, checksum FA Changes since previous release, Attributes of NonFatalPOSTError2-6 have been changed to not generate a trap and not to be logged. The default username and password of User1 & User2 have been changed. The default upper threshold of TimeOnCharge has been changed. Terminates S/W WDT when diagnostics processor captures Port80 writes. Does not terminate pass-through mode even if DTR of pass-through goes off during Pass-through value of 2. F/W exits PTM when it detects H/W break during length of ESC-seq = 0 and direct PTM is not specified. In other cases, F/W will handle the break, but if a value of 2 is specified in the pass-through variable and BIOS does not complete, F/W does not pass the break from pass-through port to modem port. F/W adds ‘F’ to LSD of LCD when F/W detects POST timeout and LSD of previous LCD code was zero. Attribute of FPSCVariableValid has been changed. Reset reason is not changed when M/B reset is executed as the result of POST execution timeout. |
| BETA 1C PN 155222SW. |
This is BETA 3.005 of the Shogun FPSC
Firmware SC Firmware Binary file name for customising EPROM => as follows; IC3 = 155083SW.BIN (even address, checksum = 8870) IC2 = 155084SW.BIN (odd address, checksum = 5D90) Binary file for FLASH upgrade => 155175SW.BIN (checksum = E600) (This will be used when FLASH upgrading function is executed by SMA. The content of this file is same as above files.) Changes Since Last Release Changed portion from previous version 3.003 => as follows; F/W doesn't turn on Security LED even if the system is in security locked state. Registered IR-card silences the alarm sound and clears LCD when security is enabled and front door is locked. F/W terminates push-button security alarm if the button is pushed for shorter than ShutdownSwitchHoldOffTime. Default attribute of BIOSVersion and SMICBIOSVersion have been changed. F/W stores monitored analog values but does not execute error checking during motherboard DC power is not provided. F/W executes reset instantly when resetting motherboard is requested and WDT over-flow or BIOS time-out occurs. F/W displays system dead code only when motherboard reset does not proceed at all. F/W accepts 0 for length byte of username and call-back number of user type variable. F/W displays its version when CTRL+SHUTDOWN+RESET are pushed repeatedly. F/W checks the existence of remote log-in user in main-loop. Default attribute setting of next variables have been changed. Boot_Device, Power_Mode, SCACVoltage, SCACCurrent User_BIOS_Version (0x0054) variable has been added. F/W copies default shutdown hold off time to reset and shutdown hold off time when it receives POST Progress code. To prevent the case of battery voltage is 0, F/W predicts DC current by assuming that battery voltage is 48000 [mV]. Default setting of battery full charge time and upper threshold of time on charge have been changed to 108000 sec. Default setting of MODEM and PassThrough port have been changed to 19200bps. Default setting of Escape Sequence has been changed to none. Direct pass through mode that is invoked from pass-through port has been deleted. Next bug of F/W has been fixed. F/W suspends trap generation to MODEM port till it receives some command when it detects power good becomes active. When battery voltage becomes too low, F/W executes power off only when the motherboard power is on. (Bug fix) F/W re-calculate time on charge when motherboard power off is done during the system is battery backed up. (Bug fix) The ways of AC voltage, current and DC current calculation have been changed based on the calibration data. MODEM related variables can be changed without executing FPSC reset. (F/W executes MODEM related hardware re-programming when MODEM user off from FPSC.) Default thresholds of DC voltage variables have been changed. F/W ticks during shutdown is in progress. F/W terminates shutdown hold off timer and reset hold off timer when it receives End Marker code, Device Driver Attached code or Client Attached code. Changed portion from previous version (3.002) => as follows; Attributes of NonFatalPOSTError2-6 are changed not to generate a trap and do not log. Default username and password of User1 and 2 have been changed. Default upper threshold of TimeOnCharge variable is changed. Terminates S/W WDT when Diag-P captures port80 writing. Do not terminate pass-through mode even if DTR of pass-through becomes off during Pass_Through's content is 2. F/W exit PTM when it detects H/W Break during length of esc-seq is zero and direct PTM is not specified. In other case, F/W will handle the break. But, if 2 is specified in the Pass_through variable and BIOS does not finish, F/W does not pass break from Passthrough port to MODEM port. Correction of mistake. F/W adds 'F' to LSD of LCD when F/W detects POST time-out and LSD of previous LCD code was zero. Attribute of FPSCVariableValid is changed. Reset reason is not changed when motherboard reset is executed as the result of POST execution time-out. PRFs/IPRs No PRFs or IPRs have been resolved with this release. |
| BETA 1D PN 155222SW. |
This is BETA 3.006 of the Shogun FPSC
Firmware Binary file name for customising EPROM => as follows; IC3 = 155083SW.BIN (even address, checksum = D9A3) IC2 = 155084SW.BIN (odd address, checksum = 825D) Binary file for customising FLASH => 155175.BIN (checksum = 5C00) (This will be also used when FLASH upgrading function is executed by SMA. The content of this file is same as above files.) Firmware version => 3.006 (Variable table = 3.006, protocol version = 2.000) Changes Since Last Release Changes from previous version (3.005) are as follows; Initial value of battery back-up table is changed. In addition to the shutdown hold off timer, F/W ticks during reset hold off timer is active. SetUpStart, FlashDiskVersion and LCDCurrentCode variables are added. SetUpStart : Choice, 0x022c, attribute1 = --------, attribute2 = -GSGS--- FlashDiskVersion : String, 0x022d, attribute1 = --------, attribute2 = - GSGS--- LCDCurrentCode : Count, 0x00e5, attribute1 = --------, attribute2 = -G-G- M-- During motherboard power is off, F/W sets fan stopped code in the FanNStatus variables without execute error checking. F/W switches off the machine only when it detects battery voltage exceeds threshold boundary and shutdown is requested in the attribute1 and circuit breaker is closed and AC good is off. Default threshold of ACVoltage variable is changed. Default attribute of AC15ALatch is changed to log and generate traps. Initial value of Latch15AAction is changed to pulse p-on signal when AC voltage is lower than 264V (always). Power off/on is added to the POST error action as follows. POSTErrorAction = 0 : Do nothing. = 1 : Sound alarm. = 2 : Sound alarm and Reset or P-off/on M/B. (Repeat Reset 2 times and p-off/on 1 time.) = 3 : Sound alarm and Reset M/B. = 4 : Sound alarm and P-off/on M/B. Default setting of POSTErrorAction is changed to alarm and its attribute1 (error acton) is changed to write log. FPSC F/W treats both 2000 and 7FF0 for NextBootStage as end of POST. In addition to time stamp, event type and variable number are cleared when AuditPointer is written to 0 by some client. To prevent confusing, the content of event log of invalid power good off always indicates PowerGood variable being false. PRFs/IPRs The following IPRs have been resolved with this release; 1397,1400, 1440, 1441, 1442, 1446, 1447, 1456. |
| BETA 2A PN 155222SW. |
Introduction This is the first beta release of version 3.007 of the Shogun FPSC processor firmware. EPROM Part No. is as follows; IC3 = 15508331 (even address) IC2 = 15508431 (odd address) Binary file name for customising EPROM => as follows; IC3 = 155083SW.BIN (even address, checksum = F30E) IC2 = 155084SW.BIN (odd address, checksum = B0F2) Binary file for customising FLASH is 155175.BIN (checksum = A400) (This will be also used when FLASH upgrading function is executed by SMA. The content of this file is same as above files.) Firmware version is 3.007, FPSC variable table version is 3.007, FPSC Client I/F Protocol version is 2.000. Changes Since Last Release FPSC F/W does not execute error action when it detects POST execution time-out and 2A70 is set in NextBootStage variable because 2A70 indicates that setup is started. FPSC F/W executes power off instead of motherboard reset when reset hold off timer expires and AC fails. FPSC F/W rings off the call when ringing up succeeded but SMA does not execute auth1 within Authenticate 1 time-out period during force trap process. FPSC F/W forces log off a user when non-zero time-out value (1 - 65535 sec) is specified in the FPSC variable and the specified period passed. Time-out value is specified in the next variables. Both initial values are zero (disabled). FPSC : FPSCUserForceTimeOut,0x00e6,count,--------,-GSGS--- MODEM : MODEMUserForceTimeOut,0x00e7,count,--------,-GSGS--- FPSC F/W does not check error condition of next signals from PSU during F/W regards power mode as Power-off mode. In that case, F/W just copies current state into FPSC variables (PSUTemperature and BatteryChargeMonitor). Signals are Thermal Alarm signal and Battery Charge Monitor signal. Logging is added to default error action setting of BatteryChargeMonitor variable. PRFs/IPRs No IPRs have been addressed with this release. Testing This version of FPSC firmware has been tested under the following conditions. Revision of hardware : SC-board = B, FP-board = D (must be D or later) Used machine : PSU simulator board and Shogun#8 of ISEC Used O/S : UnixWare Tested portion : All changed portions |
| BETA 2B PN 155222SW. |
EPROM Part No. => as follows; IC3 = 15508331 (even address) IC2 = 15508431 (odd address) Binary file name for customising EPROM => as follows; IC3 = 155083SW.BIN (even address, checksum = F6B8) IC2 = 155084SW.BIN (odd address, checksum = B047) Binary file for customising FLASH => 155175.BIN (checksum = A700) (This will be also used when FLASH upgrading function is executed by SMA. The content of this file is same as above files.) Changes Since Last Release Firmware version = 3.008, FPSC variable table version = 3.008, FPSC Client I/F Protocol version = 2.000. Changed portion from previous version 3.007 => as follows; In order to generate NMI during SMI is enabled by SCU, FPSC F/W requests diag-processor to pulse IOCHK signal instead of NMI signal. Because SMIC BIOS issues 3A30 POST progress code at that time, FPSC F/W does nothing when POST execution time-out is detected during NextBootStage code is 3A30. |
| BETA 2C PN 155222SW. |
EPROM Part Nos IC3 = 15508331 (even address) IC2 = 15508431 (odd address) Binary file name for customising EPROM IC3 = 155083SW.BIN (even address, checksum = F351) IC2 = 155084SW.BIN (odd address, checksum = F6AF) Binary file for customising FLASH 155175.BIN (checksum = EA00) (This will be also used when FLASH upgrading function is executed by SMA. The content of this file is same as above files.) Changes Since Last Release Firmware version = 3.010 FPSC variable table version = 3.010 FPSC Client I/F Protocol version = 2.000 Modem controlling problem. Setting RTC to binary mode during DO_SELF_TEST command execution. New mode for ResetConvert [=2: Power on], FPSC automatically executes power on when AC power is returned following an AC failure. |
| release 2 PN 155222SW. |
This is the REL 2 of the Shogun FPSC
processor firmware (Version 3.008). EPROM Part No. => as follows; IC3 = 15508331 (even address) IC2 = 15508431 (odd address) Binary file name for customising EPROM => as follows; IC3 = 155083SW.BIN (even address, checksum = F6B8) IC2 = 155084SW.BIN (odd address, checksum = B047) Binary file for customising FLASH => 155175.BIN (checksum = A700) (This will be also used when FLASH upgrading function is executed by SMA. The content of this file is same as above files.) Changes Since Last Release Firmware version = 3.008, FPSC variable table version = 3.008, FPSC Client I/F Protocol version = 2.000. Changed portion from previous version 3.007 => as follows; In order to generate NMI during SMI is enabled by SCU, FPSC F/W requests diag-processor to pulse IOCHK signal instead of NMI signal. Because SMIC BIOS issues 3A30 POST progress code at that time, FPSC F/W does nothing when POST execution time-out is detected during NextBootStage code is 3A30. |
| version 3.011 PN 155222SW checksum see text. |
Introduction This is Beta 3 of the Shogun FPSC processor firmware (Version 3.011). The object of this release is to provide the latest firmware to the field. This current version includes changes to prevent automatic power down of Shogun computers at 11:59 on 31/12/199? This bug is not thought to have been seen in the UK because the Japanese FT Manager is not shipped by ACL. Following is Tak Saito’s readme doc on the FPSC firmware. EPROM Part No. => as follows; IC3 = 15508331 (even address) IC2 = 15508431 (odd address) Binary file name for customising EPROM => as follows; IC3 = 155083SW.BIN (even address, checksum = F02A) IC2 = 155084SW.BIN (odd address, checksum = 05D6) Binary file for FLASH upgrade => 155175SW.BIN (checksum = F600) (This will be used when FLASH upgrading function is executed by SMA. The content of this file is same as above files.) Firmware version => 3.011 (FPSC variable table version => 3.011) (FPSC Client I/F Protocol version => 2.000) Changed portion from version 3.010 => as follows; Bug fix for scheduled power-on/off and reset. FPSC executes scheduled power-on/off or motherboard_reset instantly when FPSC detects current time having passed Next Power On / Off or Reset Time. FPSC regards year of '00 - '94 as 2000 - 2094. (In previous versions, FPSC regards year of '00 - '93 as 2000 - 2093.) Related IPR => none |
| Release 1 12/03/97 PN 155222SW |
Introduction This is a FPSC firmware release for the Shogun Server System. Binary for EVEN address EPROM (IC3): 155083SW.BIN Binary for ODD address EPROM (IC2): 155084SW.BIN Binary for FLASH ROM (IC1): 155175SW.BIN Changes Since Last Release No alterations have been made since the last beta which incorporated the following changes: Bug fix for elapsed scheduled Power-On/Off and Reset times. Compliance for turn of the century date and time. File List Disk #1 /1 Volume in drive A is 155222SW Volume Serial Number is 98EF-1F15 Directory of A:\ 11/03/97 16:36 131,072 155083SW.BIN 11/03/97 16:36 131,072 155084SW.BIN 11/03/97 16:36 131,072 155175SW.BIN 3 File(s) 393,216 bytes 1,064,448 bytes free |
