Mitsubishi Electric - Computing for a Connected World Insight CD Home Page

Products
Services
Knowledgebase
Bulletins (IPBs)
Guides
FAQs
Owner's Handbooks
Product Datasheets
Miscellaneous Items
Upgrades
Downloads
Search Insight
E-Mail us
Insight Service
Year 2000
Other Mitsubishi Sites
Site Disclaimer


Error Beep Sequences for older Apricot products

The Power On Self-Test (POST) is executed each time the computer is powered-up. The POST tests the following:

- processor system - system configuration
- memory - video system
- hard disk drive and controller - real time clock
- floppy disk drive and controller - system timer
- keyboard - correct boot disk
- ROM checksum

If all tests are completed successfully, one short beep will be heard from the loudspeaker in the system unit.

If more than one beep is heard, make a note of the sequence of beeps and refer to the table below to determine the cause of the error. As an example, the beep sequence '1-3-3' represents a single beep, followed by a group of three beeps, followed by another group of three beeps.

Beep
Sequence
Error Description
1-1-1 No video card
1-1-3 CMOS RAM read/write test failure
1-1-4 BIOS ROM checksum failure
1-2-1 Programmable interval timer failure
1-2-2 DMA initialisation failure
1-2-3 DMA page register read/write failure
1-3-1 RAM refresh verification failure
1-3-3 1st 64K RAM chip data line failure (multi-bit)
1-3-4 1st 64K RAM chip data odd/even logic failure
1-4-1 1st 64K RAM chip address line failure
1-4-2 1st 64K RAM chip parity failure
2-1-1 1st 64K RAM chip data line failure
2-1-2 1st 64K RAM chip data line failure (bit 1)
2-1-3 1st 64K RAM chip data line failure (bit 2)
2-1-4 1st 64K RAM chip data line failure (bit 3)
2-2-1 1st 64K RAM chip data line failure (bit 4)
2-2-2 1st 64K RAM chip data line failure (bit 5)
2-2-3 1st 64K RAM chip data line failure (bit 6)
2-2-4 1st 64K RAM chip data line failure (bit 7)
2-3-1 1st 64K RAM chip data line failure (bit 8)
2-3-2 1st 64K RAM chip data line failure (bit 9)
2-3-3 1st 64K RAM chip data line failure (bit A)
2-3-4 1st 64K RAM chip data line failure (bit B)
2-4-1 1st 64K RAM chip data line failure (bit C)
2-4-2 1st 64K RAM chip data line failure (bit D)
2-4-3 1st 64K RAM chip data line failure (bit E)
2-4-4 1st 64K RAM chip data line failure (bit F)
3-1-1 Slave DMA register failure
3-1-2 Master DMA register failure
3-1-3 Master interrupt mask register failure
3-1-4 Slave interrupt mask register failure
3-2-4 Keyboard controller failure
3-3-4 Screen memory failure
3-4-1 Screen initialisation failure
3-4-2 Screen retrace test failure
4-2-1 Timer tick interrupt failure
4-2-2 Shutdown failure
4-2-3 Gate A20 failure
4-2-4 Unexpected interrupt in protected mode
4-3-1 RAM failure address 010000H to 0A0000H
4-3-3 Interval timer channel 2 fail
4-3-4 Time of day clock failure
4-4-1 Serial port test in progress or failure
4-4-2 Parallel port test in progress or failure
4-4-3 Maths co-processor test in progress or failure
There is also a group of error beep codes which are preceded by a lower frequency tone (signified below by 'L').
L-1-1-0 VGA failure
L-1-1-1 Video DAC failure
L-1-1-2 System board select failure
L-1-1-3 Extended CMOS RAM failure



Back to Top Back to Top


 

Computing for a Connected World